# US 2026/0089979 A1 · Semiconductor device and electronic system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0089979 A1 - Document ID: US20260089979A1 - Status: Published application - Kind: A1 - Application number: 19/094,012 - Filed: 2025-03-28 - Published: 2026-03-26 - Earliest claimed: 2024-09-25 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sejie TAKAKI; Seunghyun Lee; Kyungdong Kim; Jeehoon Han - Web page: https://patentgrep.com/patent/US20260089979A1 ## CPC - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 90/00: Package configurations - H10W 90/792: {between multiple chips} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device according to an embodiment includes a circuit region; and a cell region stacked on the circuit region, wherein the cell region comprises a plurality of memory groups, wherein each of the plurality of memory groups comprises a plurality of memory portions, wherein a first plurality of memory portions in a first memory group from the plurality of memory groups are connected to through a first wiring connection, and wherein the first memory group among the plurality of memory groups is connected to a second memory group among the plurality of memory groups through a second wiring connection different from the first wiring connection. ## Claims ### Claim 1 A semiconductor device, comprising: a circuit region; and a cell region stacked on the circuit region, wherein the cell region comprises a plurality of memory groups, wherein each of the plurality of memory groups comprises a plurality of memory portions, wherein a first plurality of memory portions in a first memory group from the plurality of memory groups are connected to through a first wiring connection, and wherein the first memory group among the plurality of memory groups is connected to a second memory group among the plurality of memory groups through a second wiring connection different from the first wiring connection. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first plurality of memory portions comprises a first plurality of driving lines, wherein the first plurality of driving lines comprise a first plurality of word lines and a first plurality of bit lines, wherein the first plurality of bit lines extend in a direction intersecting the first plurality of word lines, wherein the first wiring connection is one of: a word-line connection in which corresponding word lines of the first plurality of word lines are connected, a bit-line connection in which corresponding bit lines of the first plurality of bit lines are connected, and an integrated connection in which the corresponding word lines are connected and the corresponding bit lines are connected, and wherein the second wiring connection is another connection from the word-line connection, the bit-line connection, and the integrated connection, that is different than the first wiring connection. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein corresponding driving lines of the first plurality of driving lines in the first plurality of memory portions are connected to a same wiring or are connected to a same transistor using the first wiring connection, and wherein corresponding driving lines in the plurality of memory groups are connected to a same wiring or are connected to a same transistor by the second wiring connection. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein each of the first plurality of memory portions comprises: a gate stack that comprises a plurality of gate electrodes, the plurality of gate electrodes being spaced apart from each other while interposing an interlayer insulation layer and forming the first plurality of word lines; a plurality of channels that pass through or penetrate the gate stack and are connected to the first plurality of bit lines; an upper wiring portion disposed at an upper portion of the gate stack and a lower wiring portion disposed at a lower portion of the gate stack; and a penetrating plug that passes through the gate stack or is disposed outside the gate stack, the penetrating plug electrically connecting the upper wiring portion and the lower wiring portion to corresponding driving lines of the first plurality of driving lines in at least one of the first plurality of memory portions or the plurality of memory groups. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the penetrating plug comprises: a conductive portion, and a side insulation layer on a side surface of the conductive portion. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein the penetrating plug comprises a word plug configured to electrically connect the corresponding word lines in the first plurality of memory portions or the plurality of memory groups. ### Claim 7 (depends on 4) The semiconductor device of claim 4, wherein the penetrating plug comprises a bit plug configured to electrically connect the corresponding bit lines in the first plurality of memory portions or the plurality of memory groups. ### Claim 8 (depends on 2) The semiconductor device of claim 2, wherein the first wiring connection is the integrated connection, and the second wiring connection is the word-line connection or the bit-line connection. ### Claim 9 (depends on 2) The semiconductor device of claim 2, wherein the first wiring connection is the bit-line connection, and the second wiring connection is the word-line connection or the integrated connection. ### Claim 10 (depends on 2) The semiconductor device of claim 2, wherein the first wiring connection is the word-line connection, and the second wiring connection is the bit-line connection or the integrated connection. ### Claim 11 (depends on 2) The semiconductor device of claim 2, further comprising: a word connection wiring that is connected to the corresponding word lines and is shared in the first plurality of memory portions; a bit connection wiring that is connected to the corresponding bit lines in at least two memory portions among the first plurality of memory portions; and an additional bit connection wiring that is connected to the corresponding bit lines in at least two other memory portions among the first plurality of memory portions. ### Claim 12 (depends on 2) The semiconductor device of claim 2, further comprising: a bit connection wiring that is connected to the corresponding bit lines, the bit connection wiring being shared in the first plurality of memory portions, a word connection wiring that is connected to the corresponding word lines in at least two memory portions among the first plurality of memory portions, and an additional word connection wiring that is connected to the corresponding word lines in at least two other memory portions among the first plurality of memory portions. ### Claim 13 (depends on 2) The semiconductor device of claim 2, further comprising: a word connection wiring that is connected to the corresponding word lines in at least two first memory portions among the first plurality of memory portions; an additional word connection wiring that is connected to the corresponding word lines in at least two other first memory portions among the first plurality of memory portions; a bit connection wiring that is connected to the corresponding bit lines in at least two second memory portions among the first plurality of memory portions; and an additional bit connection wiring that is connected to the corresponding bit lines in at least two other second memory portions among the first plurality of memory portions. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein a memory cell block is associated with a part of the plurality of memory groups to be associated with one or more memory portions. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the memory cell block is associated with each of the plurality of memory portions. ### Claim 16 (depends on 1) The semiconductor device of claim 1, wherein more than one memory portion of the plurality of memory portions in the plurality of memory groups are stacked on each other in a thickness direction, and wherein the circuit region and the plurality of memory portions are bonded by hybrid bonding. ### Claim 17 A semiconductor device, comprising: a circuit region and a cell region stacked on the circuit region, wherein the cell region comprises a plurality of memory sets, wherein each of the plurality of memory sets comprises a plurality of memory groups, wherein each of the plurality of memory groups comprises a plurality of memory portions, and wherein a first plurality of memory portions in a first memory group from the plurality of memory groups are connected to through a first wiring connection, wherein the first memory group among the plurality of memory groups is connected to a second memory group among the plurality of memory groups through a second wiring connection different from the first wiring connection in each of the memory set, and wherein the plurality of memory sets are connected to each other through a third wiring connection different from the second wiring connection. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the third wiring connection is different from the first wiring connection. ### Claim 19 (depends on 17) The semiconductor device of claim 17, wherein the first plurality of memory portions comprises a first plurality of driving lines, wherein the first plurality of driving lines comprise a first plurality of word lines and a first plurality of bit lines, wherein the first plurality of bit lines extend in a direction intersecting the first plurality of word lines, wherein the first wiring connection is one of: a word-line connection in which corresponding word lines of the first plurality of word lines are connected, a bit-line connection in which corresponding bit lines of the first plurality of bit lines are connected, and an integrated connection in which the corresponding word lines are connected and the corresponding bit lines are connected, wherein the second wiring connection is another connection among the word-line connection, the bit-line connection, and the integrated connection, and wherein the third wiring connection structure is another connection among the word-line connection, the bit-line connection, and the integrated connection. ### Claim 20 An electronic system, comprising: a main substrate; a semiconductor device on the main substrate; and a controller connected to the semiconductor device on the main substrate, wherein the semiconductor device comprises a circuit region and a cell region stacked on the circuit region, wherein the cell region comprises a plurality of memory groups, wherein each of the plurality of memory groups comprises a plurality of memory portions, wherein a first plurality of memory portions in a first memory group from the plurality of memory groups are connected to through a first wiring connection, and wherein the first memory group among the plurality of memory groups is connected to a second memory group among the plurality of memory groups through a second wiring connection different from the first wiring connection.