Fpga data transfer over network-on-chip (noc)

Abstract

Data transfer over a packet-based network-on-chip (NoC) of an integrated circuit device, including an example in which a first region of programmable logic (PL) serves as a first interface circuit between a first circuit block and a NoC master unit (NMU), to receive first and second data via respective first and second channels of the first circuit block based on a communication protocol of the first circuit block, concatenate the first and second data to provide the concatenated content, and transmit the concatenated content to the NMU. The NoC may route the packets from the NMU to a NoC slave unit (NSU) associated with a second circuit block via a pre-determined route of the NoC that is dedicated to traffic between the first and second circuit blocks. A second region of the PL serves as an interface circuit between the NSU and the second block to unpack the data.

Dependencies are inferred from the claim text.