# US 2026/0088097 A1 · Pre-read operation for multi-pass programming of memory devices

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- Number: US 2026/0088097 A1
- Document ID: US20260088097A1
- Status: Published application
- Kind: A1
- Application number: 19/405,209
- Filed: 2025-12-01
- Published: 2026-03-26
- Earliest claimed: 2022-03-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Nagendra Prasad Ganesh Rao; Sead Zildzic, JR.
- Web page: https://patentgrep.com/patent/US20260088097A1

## CPC

- G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/20: Initialising; Data preset; Chip identification
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 29/50004: {of threshold voltage}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first program pass of a multi-pass program operation to partially program one or more memory cells of the memory array to a first program level that is different than a final program level. The operations include causing a pre-read operation to read data corresponding to the first program pass. The operations further include determining an updated second program voltage of a second program pass of the multi-pass program operation based on the pre-read operation.

## Claims

### Claim 1

An apparatus comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first program pass of a multi-pass program operation to partially program one or more memory cells of the memory array to a first program level that is different than a final program level;
causing a pre-read operation to read data corresponding to the first program pass; and
determining an updated second program voltage of a second program pass of the multi-pass program operation based on the pre-read operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the pre-read operation is performed subsequent to the first program pass of the multi-pass program operation.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein determining the updated second program voltage of the second program pass comprises:
determining, based on the pre-read operation, whether a shift of a threshold voltage (VT) corresponding to the one or more memory cells satisfies a condition related to a VT change, wherein the updated second program voltage is determined based on the shift in VT satisfying the condition related to the VT change.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the operations further comprise:
causing the second program pass of the multi-pass program operation to be performed at the memory array using the updated second program voltage.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein the operations further comprise:
responsive to determining that the shift of the VT corresponding to the one or more memory cells does not satisfy the condition, causing the second program pass of the multi-pass program operation to be performed at the memory array using a default second program voltage.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein causing the pre-read operation to be performed to read the data corresponding to the first program pass, comprises:
reading data corresponding to a particular distribution of a plurality of distributions that are associated with the one or more memory cells, wherein the one or more memory cells comprise multi-bit memory cells.

### Claim 7 (depends on 3)

The apparatus of claim 3, wherein determining whether the shift of the VT corresponding to the one or more memory cells satisfies the condition related to the VT change based on the pre-read operation, comprises:
determining an error count based on the data read from the pre-read operation; and
determining whether the error count exceeds a threshold error count.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein determining the updated second program voltage of the second program pass of the multi-pass program operation, comprises:
identifying a record that identifies a plurality of updated second program voltages; and
selecting the updated second program voltage from the plurality of updated second program voltages based on the data read from the pre-read operation.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein determining the updated second program voltage of the second program pass of the multi-pass program operation, comprises:
identifying a model associated with a plurality of second program voltages; and
identifying the updated second program voltage from output of the model, wherein input to the model corresponds to the data read from the pre-read operation.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the memory array and the control logic are encased in a single integrated circuit package.

### Claim 11

A method comprising:
causing a first program pass of a multi-pass program operation to partially program one or more memory cells of a memory array to a first program level that is different than a final program level;
causing a pre-read operation to read data corresponding to the first program pass; and
determining an updated second program voltage of a second program pass of the multi-pass program operation based on the pre-read operation.

### Claim 12 (depends on 11)

The method of claim 11, wherein the pre-read operation is performed subsequent to the first program pass of the multi-pass program operation.

### Claim 13 (depends on 11)

The method of claim 11, wherein determining the updated second program voltage of the second program pass comprises: determining, based on the pre-read operation, whether a shift of a threshold voltage (VT) corresponding to the one or more memory cells satisfies a condition related to a VT change, wherein the updated second program voltage is determined based on the shift in VT satisfying the condition related to the VT change.

### Claim 14 (depends on 11)

The method of claim 11, further comprising: causing the second program pass of the multi-pass program operation to be performed at the memory array using the updated second program voltage.

### Claim 15 (depends on 13)

The method of claim 13, further comprising: responsive to determining that the shift of the VT corresponding to the one or more memory cells does not satisfy the condition, causing the second program pass of the multi-pass program operation to be performed at the memory array using a default second program voltage.

### Claim 16

A memory device, comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first program pass of a multi-pass program operation to partially program one or more memory cells of the memory array to a first program level that is different than a final program level;
causing a pre-read operation to read data corresponding to the first program pass; and
determining an updated second program voltage of a second program pass of the multi-pass program operation based on the pre-read operation.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein the pre-read operation is performed subsequent to the first program pass of the multi-pass program operation.

### Claim 18 (depends on 16)

The memory device of claim 16, wherein determining the updated second program voltage of the second program pass comprises: determining, based on the pre-read operation, whether a shift of a threshold voltage (VT) corresponding to the one or more memory cells satisfies a condition related to a VT change, wherein the updated second program voltage is determined based on the shift in VT satisfying the condition related to the VT change.

### Claim 19 (depends on 16)

The memory device of claim 16, wherein the operations further comprise: causing the second program pass of the multi-pass program operation to be performed at the memory array using the updated second program voltage.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein the operations further comprise: responsive to determining that the shift of the VT corresponding to the one or more memory cells does not satisfy the condition, causing the second program pass of the multi-pass program operation to be performed at the memory array using a default second program voltage.