# US 2026/0088084 A1 · Compute-in-memory arrays

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- Number: US 2026/0088084 A1
- Document ID: US20260088084A1
- Status: Published application
- Kind: A1
- Application number: 18/896,392
- Filed: 2024-09-25
- Published: 2026-03-26
- Earliest claimed: 2024-09-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Moritz Voelker; Peter Baumgartner
- Web page: https://patentgrep.com/patent/US20260088084A1

## CPC

- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/003: {Cell access}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments herein relate to compute-in-memory. In one aspect, memory cells in an array include a larger, primary element and a smaller, secondary element in parallel. The memory cells are phase-change memory (PCM) cells in an example implementation. The second elements are pre-programmed to narrow a conductivity distribution of a column of cells. The pre-programming is based on a measured conductivity distribution of the primary elements of the column. In another aspect, selected memory cells in an array are read using an alternating current (AC) signal which reduces sensing noise. Different bit lines can receive signals with different frequencies and/or amplitudes.

## Claims

### Claim 1

An apparatus, comprising:
an array of memory cells in a plurality of rows and a plurality of columns; and
bit lines and select lines associated with the array, wherein a memory cell in the array comprises a primary element coupled to a respective bit line and a respective select line, and a secondary element coupled to the respective bit line and the respective select line, in parallel with the primary element.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a first access transistor in series with the primary element;
a second access transistor in series with the secondary element;
a first control line coupled to a control gate of the first access transistor; and
a second control line coupled to a control gate of the second access transistor.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the memory cell is in a column of the plurality of columns;
respective memory cells of the column comprise respective primary and secondary elements coupled in parallel;
a first control line is coupled to control gates of access transistors of the respective primary elements; and
a second control line is coupled to control gates of access transistors of the respective secondary elements.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the primary and secondary elements are phase-change elements.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the primary and secondary elements are floating gate metal-oxide-semiconductor field-effect transistors (MOSFETs).

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the secondary element is smaller in size than the primary element.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the secondary element has a smaller conductivity than the primary element when the primary and secondary elements are biased by the respective bit line and the respective select line.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the array of memory cells, the bit lines and the select lines are is provided in at least one of an integrated circuit, a System on Chip, a System in Package or a computing device.

### Claim 9

A system, comprising:
an array of memory cells in plurality of rows and a plurality of columns, wherein respective memory cells of a column of the plurality of columns comprise respective primary and secondary elements coupled in parallel;
a memory capable of storing instructions; and
a processor capable of executing the instructions to:
program the primary elements and disable the secondary elements;
measure a current in the column through the primary elements; and
program the secondary elements based on the measuring and disable the primary elements.

### Claim 10 (depends on 9)

The system of claim 9, wherein the processor is capable of executing the instructions to reset the primary and secondary elements before the programming of the primary elements.

### Claim 11 (depends on 9)

The system of claim 9, wherein the programming of the primary and secondary elements comprises one-shot programming.

### Claim 12 (depends on 9)

The system of claim 9, wherein the processor is capable of executing the instructions to determine at least one of an amplitude or a duration of a program pulse to for the programming of the secondary elements.

### Claim 13 (depends on 9)

The system of claim 9, wherein the measuring comprises determining a delta by which a conductivity of the primary elements is below a target value.

### Claim 14 (depends on 13)

The system of claim 13, wherein the processor is capable of executing the instructions to determine at least one of an amplitude or a duration of a program pulse based on the delta for the programming of the secondary elements.

### Claim 15 (depends on 9)

The system of claim 9, further comprising:
a first control line coupled to control gates of access transistors of the respective primary elements of the column of memory cells; and
a second control line coupled to control gates of access transistors of the respective secondary elements of the column of memory cells.

### Claim 16 (depends on 9)

The system of claim 9, wherein the primary and secondary elements are resistive-switching elements.

### Claim 17

An apparatus, comprising:
a row driver circuit cable of applying an alternating-current (AC) signal comprising positive and negative voltages to a bit line of a memory array, wherein the bit line is coupled to one or more memory cells in the memory array; and
a column circuit to sense a current in one or more select lines coupled to the one or more memory cells in the memory array, to perform a compute-in-memory operation in the memory array.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein:
the AC signal is a first AC signal;
the bit line is a first bit line;
the row driver circuit is cable of applying a second AC signal to a second bit line of the memory array;
the first AC signal has a first frequency; and
the second AC signal has a second frequency, different than the first frequency.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the column circuit comprises a frequency-selective sense circuit.

### Claim 20 (depends on 17)

The apparatus of claim 17, wherein:
the AC signal is a first AC signal;
the bit line is a first bit line;
the row driver circuit is cable of applying a second AC signal to a second bit line of the memory array; and
the second AC signal has a different amplitude than the first AC signal.