Semiconductor memory device

A method of manufacturing a semiconductor memory device, said method comprising:

• forming a first stacked film in which a plurality of first sacrificial layers and a plurality of first insulating layers are alternately stacked one on top of another in a first direction and extend in a second direction intersecting the first direction and a third direction intersecting the first direction and the second direction;
• forming a first hole through the first stacked film;
• forming a first block insulating film, a first charge storage film, a first tunnel insulating film, a first channel semiconductor film, and a stack of three first core insulating films in order from an inner surface of the first hole;
• removing the first sacrificial layers and depositing first conductive layers at locations where the first sacrificial layers have been removed;
• forming a second stacked film in which a plurality of second sacrificial layers and a plurality of second insulating layers are alternately stacked one on top of another in the first direction and extend in a second direction intersecting the first direction and a third direction intersecting the first direction and the second direction;
• forming a second hole through the second stacked film;
• forming a second block insulating film, a second charge storage film, a second tunnel insulating film, a second channel semiconductor film, and a second core insulating film in order from an inner surface of the second hole;
• and
• removing the second sacrificial layers and depositing second conductive layers at locations where the second sacrificial layers have been removed.

A method of performing operations in a semiconductor memory device comprising:

• a first stacked film in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one on top of another in a first direction and extend in a second direction intersecting the first direction and a third direction intersecting the first direction and the second direction;
• a first core insulating film penetrating the first stacked film in the first direction and containing an oxide;
• a second core insulating film provided around the first core insulating film, penetrating the first stacked film in the first direction, and including a nitride;
• a third core insulating film provided around the second core insulating film, penetrating the first stacked film in the first direction, and containing an oxide;
• a first channel semiconductor film provided around the third core insulating film and penetrating the first stacked film in the first direction;
• a first tunnel insulating film provided around the first channel semiconductor film and penetrating the first stacked film in the first direction;
• a first charge storage film provided around the first tunnel insulating film and penetrating the first stacked film in the first direction;
• a second stacked film in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked one on top of another in a first direction and extend in the second and third directions;
• a fourth core insulating film penetrating the second stacked film in the first direction and containing an oxide;
• a second channel semiconductor film provided around the fourth core insulating film and penetrating the second stacked film in the first direction;
• a second tunnel insulating film provided around the second channel semiconductor film and penetrating the second stacked film in the first direction;
• and
• a second charge storage film provided around the second tunnel insulating film and penetrating the second stacked film in the first direction, wherein a write operation performed on first memory cells that are along the first channel semiconductor film and second memory cells that are along the second channel semiconductor film, comprises the steps of:
• programming the first memory cells to one of 2N1 threshold voltage levels;
• and
• programming the second memory cells to one of 2N2 threshold voltage levels, where N2<N1.