# US 2026/0086933 A1 · Chip and its memory management method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0086933 A1 - Document ID: US20260086933A1 - Status: Published application - Kind: A1 - Application number: 19/314,024 - Filed: 2025-08-29 - Published: 2026-03-26 - Earliest claimed: 2024-09-24 - Assignees: Sigmastar Technology Ltd. - Applicants: Sigmastar Technology Ltd. - Inventors: Xuelin Ye; Wenshuai Xi - Web page: https://patentgrep.com/patent/US20260086933A1 ## CPC - G06F 12/023: {Free address space management} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 2212/1016: Performance improvement - G06F 2212/657: Virtual address space management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A chip is connected to a memory that includes a memory section composed of multiple memory blocks. The chip includes a memory management circuit and a computing circuit. The computing circuit, connected to both the memory and the memory management circuit, is configured to execute a memory management driver to perform the following steps: receiving a memory request; searching a memory region for at least one free memory block according to a memory region linked list containing a node corresponding to the memory region, where the memory region is a part of the memory section; and using the memory management circuit to perform memory mapping on the at least one free memory block found. ## Claims ### Claim 1 A chip coupled to a memory, the memory comprising a memory section, the memory section comprising a plurality of memory blocks, the chip comprising: a memory management circuit; and a computing circuit coupled to the memory and the memory management circuit, and configured to execute a memory management driver to perform following steps: receiving a memory request; searching a memory region for at least one free memory block according to a memory region linked list, wherein the memory region linked list contains a node corresponding to the memory region, and the memory region is a part of the memory section; and performing memory mapping on the at least one free memory block found via the memory management circuit. ### Claim 2 (depends on 1) The chip of claim 1, wherein the node is a first node, the memory region is a first memory region, and the computing circuit further performs following steps: creating a second node in the memory region linked list when a total size of the at least one free memory block found is smaller than a requested memory size of the memory request, wherein the second node corresponds to a second memory region, and the second memory region is a part of the memory section and comprises a plurality of memory blocks and an allocated memory block; and performing mapping on the allocated memory block via the memory management circuit. ### Claim 3 (depends on 2) The chip of claim 2, wherein the total size is a first total size, and a sum of the first total size and a second total size of the allocated memory block is equal to the requested memory size. ### Claim 4 (depends on 2) The chip of claim 2, wherein the first memory region and the second memory region are allocated by a contiguous memory allocator. ### Claim 5 (depends on 1) The chip of claim 1, wherein the node comprises a list of free memory blocks, and the list of free memory blocks points to the at least one free memory block found. ### Claim 6 (depends on 5) The chip of claim 5, wherein the step of searching the memory region for the at least one free memory block according to the memory region linked list includes visiting the list of free memory blocks. ### Claim 7 (depends on 5) The chip of claim 5, wherein the memory region comprises a plurality of allocated memory blocks, and the computing circuit further performs following steps: inserting a plurality of memory block structures corresponding to the plurality of allocated memory blocks into the list of free memory blocks to release the plurality of allocated memory blocks. ### Claim 8 (depends on 7) The chip of claim 7, wherein the computing circuit further performs following steps: removing the node from the memory region linked list when all of the plurality of allocated memory blocks of the node have been released. ### Claim 9 (depends on 8) The chip of claim 8, wherein the node comprises a reference count, and the computing circuit further performs following steps: determining whether all of the plurality of allocated memory blocks of the node have been released according to the reference count. ### Claim 10 (depends on 1) The chip of claim 1, wherein the memory region is an integer multiple of a minimum allocation size, and when a total size of the at least one free memory block found is greater than or equal to a requested memory size of the memory request, the requested memory size is not adjusted to an integer multiple of the minimum allocation size. ### Claim 11 A memory management method applied to a memory, the memory comprising a memory section, the memory section comprising a plurality of memory blocks, the method comprising: receiving a memory request; searching a memory region for at least one free memory block according to a memory region linked list, wherein the memory region linked list contains a node corresponding to the memory region, and the memory region is a part of the memory section; and performing memory mapping on the at least one free memory block found via the memory management circuit. ### Claim 12 (depends on 11) The method of claim 11, wherein the node is a first node, the memory region is a first memory region, and the method further comprises: creating a second node in the memory region linked list when a total size of the at least one free memory block found is smaller than a requested memory size of the memory request, wherein the second node corresponds to a second memory region, and the second memory region is a part of the memory section and comprises a plurality of memory blocks and an allocated memory block; and performing mapping on the allocated memory block via the memory management circuit. ### Claim 13 (depends on 12) The method of claim 12, wherein the total size is a first total size, and a sum of the first total size and a second total size of the allocated memory block is equal to the requested memory size. ### Claim 14 (depends on 11) The method of claim 11, wherein the node contains a list of free memory blocks, the list of free memory blocks points to the at least one free memory block found, and the step of searching the memory region for the at least one free memory block according to the memory region linked list visits the list of free memory blocks. ### Claim 15 (depends on 14) The method of claim 14, wherein the memory region comprises a plurality of allocated memory blocks, and the method further comprises: inserting a plurality of memory block structures corresponding to the plurality of allocated memory blocks into the list of free memory blocks to release the plurality of allocated memory blocks. ### Claim 16 (depends on 15) The method of claim 15 further comprising: removing the node from the memory region linked list when all of the plurality of allocated memory blocks of the node have been released. ### Claim 17 (depends on 16) The method of claim 16, wherein the node comprises a reference count, and the method further comprises: determining whether all of the plurality of allocated memory blocks of the node have been released according to the reference count. ### Claim 18 (depends on 11) The method of claim 11, wherein the memory region is an integer multiple of a minimum allocation size, and when a total size of the at least one free memory block found is greater than or equal to a requested memory size of the memory request, the requested memory size is not adjusted to an integer multiple of the minimum allocation size.