Interrupt register stacking within a data processing system
AssigneeNXP B.V.
InventorsChristian Herber, Jean-Baptiste Brelot
Life of this patent
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Abstract
A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.
Claims20
A processor, comprising:
- fetch circuitry configured to fetch instructions, wherein the fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt;
- and
- a speculation control circuit configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, wherein a register tracking value is updated with each speculative push.
In a processor, a method comprising:
- receiving a first interrupt during execution of a main program;
- in response to the receiving the first interrupt:
- initiating a fetch of a first interrupt handler instruction for the first interrupt, and
- initiating speculative pushing of general purpose registers (GPRs) onto a memory stack in accordance with a predetermined register order, wherein at least one GPR is speculatively pushed prior to completion of the fetch of the first interrupt handler instruction for the first interrupt;
- incrementing a register tracking value with each GPR that is speculatively pushed;
- completing the fetch of the first interrupt handler instruction, wherein the first interrupt handler instruction comprises a register push instruction which indicates a number of GPRs to be pushed for handling the first interrupt;
- and
- non-speculatively pushing GPRs in response to the register push instruction onto the memory stack in accordance with the predetermined register order while a total number of speculatively and non-speculatively pushed GPRs is less than the number of GPRs indicated by the register push instruction, wherein the register tracking value is further incremented with each GPR that is non-speculatively pushed.
Dependencies are inferred from the claim text.