# US 2026/0086597 A1 · Systems and methods for reducing power leakage in a system-on-a-chip (soc) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0086597 A1 - Document ID: US20260086597A1 - Status: Published application - Kind: A1 - Application number: 18/893,743 - Filed: 2024-09-23 - Published: 2026-03-26 - Earliest claimed: 2024-09-23 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Dinesh Kumar CHOUDHARY; Sai Sneha Venkata YESANTARAO; Raja Simha REVANURU; Chandan AGARWALLA - Web page: https://patentgrep.com/patent/US20260086597A1 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/3237: by disabling clock generation or distribution - G06F 1/324: by lowering clock frequency - G06F 1/3243: {Power saving in microcontroller unit} - G06F 1/3296: by lowering the supply or operating voltage - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems and methods are provided for reducing power consumption in an SoC by reducing the clock frequency of a cluster of processing cores or by reducing both the clock frequency and the supply voltage of the cluster when the cluster is in clock gating mode. With existing clock gating processes used in SoCs, if a cluster is in clock gating mode, the clock is still running at the same speed as when ungated, which results in significant power leakage. If the clock is running at a higher speed when the cluster is in clock gating mode, more power leakage will occur than if the clock is running at a lower speed when the cluster is in clock gating mode. By reducing the clock frequency of the cluster when it is in clock gating mode, a substantial reduction in power leakage can be realized. ## Claims ### Claim 1 A method for reducing power leakage in a system-on-a-chip (SoC), the method comprising: determining when at least a first cluster of processing cores has entered a cluster clock gating state; and in response to determining that the first cluster has entered the cluster clock gating state, reducing a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency. ### Claim 2 (depends on 1) The method of claim 1, further comprising: determining when the first cluster of processing cores has exited the cluster clock gating state; and in response to determining that the first cluster has exited the cluster clock gating state, increasing the clock frequency used by the processing cores of the first cluster from the second clock frequency to the first clock frequency. ### Claim 3 (depends on 1) The method of claim 1, further comprising: in response to determining that the first cluster has entered the cluster clock gating state, reducing a supply voltage used by the processing cores of the first cluster from a first supply voltage to a second supply voltage, the second supply voltage being less than the first supply voltage. ### Claim 4 (depends on 3) The method of claim 3, further comprising: in response to determining that the first cluster has exited the cluster clock gating state, increasing the supply voltage used by the processing cores of the first cluster from the second supply voltage to the first supply voltage. ### Claim 5 (depends on 3) The method of claim 3, wherein the first cluster comprises a plurality of processing cores and a plurality of respective core state machines, each core state machine performing power management for the respective processing core, and wherein the first cluster further comprises: a cluster state machine that performs power management for the first cluster; a firmware processor running firmware; and a dynamic voltage and frequency scaling (DVFS) state machine, and wherein the core power state machines send an aggregated notification to the cluster power state machine to notify the cluster power state machine when the processing cores are all in an idle, low power, state, and wherein the step of determining when the first cluster has entered the cluster clock gating state includes detecting that the aggregated notification has been received by the cluster power state machine. ### Claim 6 (depends on 5) The method of claim 5, wherein the step of responding to the determination that the first cluster has entered the cluster clock gating state comprises: with the cluster power state machine, sending an interrupt signal from the cluster power state machine to the firmware processor; in the firmware processor, receiving the interrupt signal, entering a power (P) state associated with the second clock frequency and the second supply voltage and outputting a signal to the DVFS state machine; and in the DVFS state machine, receiving the signal output from the firmware processor and outputting a signal that causes circuitry of the first cluster to select the second clock frequency and second supply voltage for use by the processing cores. ### Claim 7 (depends on 1) The method of claim 1, wherein the step of determining when the first cluster of processing cores has entered the cluster clock gating state comprises: determining whether all of the processing cores are in an idle, low power, state and whether at least one of the processing cores is in a core clock gating state, wherein in response to determining that all of the processing cores are in an idle, low power, state and that at least one of the processing cores is in a core clock gating state, a determination is made that the first cluster has entered the cluster clock gating state. ### Claim 8 (depends on 1) The method of claim 1, wherein the step of determining when the first cluster of processing cores has entered the cluster clock gating state comprises: determining whether all of the processing cores are in a collapsed, low power, state and whether software aggregation is being performed at a processing core level and not at a cluster level, wherein in response to determining that all of the processing cores are in a collapsed, low power, state and that software aggregation is being performed at a processing core level and not at a cluster level, a determination is made that the first cluster has entered the cluster clock gating state. ### Claim 9 A power management system for reducing power leakage in a system-on-a-chip (SoC), the system comprising: processing logic configured to: determine when at least a first cluster of processing cores has entered a cluster clock gating state; and in response to determining that the first cluster has entered the cluster clock gating state, reduce a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency. ### Claim 10 (depends on 9) The power management system of claim 9, wherein the processing logic is further configured to: determine when the first cluster of processing cores has exited the cluster clock gating state; and in response to determining that the first cluster has exited the cluster clock gating state, increase the clock frequency used by the processing cores of the first cluster from the second clock frequency to the first clock frequency. ### Claim 11 (depends on 9) The power management system of claim 9, wherein the processing logic is further configured to: in response to determining that the first cluster has entered the cluster clock gating state, reduce a supply voltage used by the processing cores of the first cluster from a first supply voltage to a second supply voltage, the second supply voltage being less than the first supply voltage. ### Claim 12 (depends on 11) The power management system of claim 11, wherein the processing logic is further configured to: in response to determining that the first cluster has exited the cluster clock gating state, increase the supply voltage used by the processing cores of the first cluster from the second supply voltage to the first supply voltage. ### Claim 13 (depends on 11) The power management system of claim 11, wherein the processing logic comprises: a plurality of core power state machines, each of the core power state machines being configured to perform power management for a respective processing core of said plurality of processing cores and to output a respective notification signal indicating when the respective processing core is in an idle, low power, state; a cluster state machine configured to perform power management for the first cluster, and wherein the cluster power state machine is configured to determine when the first cluster has entered the cluster clock gating state by detecting when an aggregate of the notification signals has been received by the cluster power state machine indicating that all of the processing cores are in the idle, low power, state, the cluster power state machine being configured to output an interrupt signal when the aggregate of the notification signals is received by the cluster power state machine; a firmware processor configured to run firmware that performs power management operations in response to receiving the interrupt signal output by the cluster power state machine; and a dynamic voltage and frequency scaling (DVFS) state machine configured to receive an output signal from the firmware processor in response to the firmware processor receiving the interrupt signal, the DVFS state machine being configured to, based at least in part on the output signal received from the firmware processor, generate an output signal that causes circuitry of the cluster to select the second clock frequency and second supply voltage for use by the processing cores. ### Claim 14 (depends on 9) The power management system of claim 9, wherein the processing logic is configured to determine when the first cluster of processing cores has entered the cluster clock gating state by: determining whether all of the processing cores are in an idle, low power, state and whether at least one of the processing cores is in a core clock gating state, wherein in response to determining that all of the processing cores are in an idle, low power, state and that at least one of the processing cores is in a core clock gating state, a determination is made by the processing logic that the first cluster has entered the cluster clock gating state. ### Claim 15 (depends on 9) The power management system claim 9, wherein the processing logic is configured to determine when the first cluster of processing cores has entered the cluster clock gating state by: determining whether all of the processing cores are in a collapsed, low power, state and whether software aggregation is being performed at a processing core level and not at a cluster level, wherein in response to determining that all of the processing cores are in a collapsed, low power, state and that software aggregation is being performed at a processing core level and not at a cluster level, a determination is made by the processing logic that the first cluster has entered the cluster clock gating state. ### Claim 16 A computer program for controlling a power management system in a system-on-a-chip (SoC) to perform power management, the computer program being embodied on a non-transitory computer readable medium and comprising computer instructions for execution by one or more processors, the computer instructions comprising: a first set of computer instructions for determining when at least a first cluster of processing cores has entered a cluster clock gating state; and a second set of computer instructions for, in response to determining that the first cluster has entered the cluster clock gating state, reducing a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency. ### Claim 17 (depends on 16) The computer program of claim 16, further comprising: a third set of computer instructions for determining when the first cluster of processing cores has exited the cluster clock gating state; and a fourth set of computer instructions for, in response to determining that the first cluster has exited the cluster clock gating state, increasing the clock frequency used by the processing cores of the first cluster from the second clock frequency to the first clock frequency. ### Claim 18 (depends on 16) The computer program of claim 16, further comprising: a third set of computer instructions for, in response to determining that the first cluster has entered the cluster clock gating state, reducing a supply voltage used by the processing cores of the first cluster from a first supply voltage to a second supply voltage, the second supply voltage being less than the first supply voltage. ### Claim 19 (depends on 18) The computer program of claim 18, further comprising: a fourth set of computer instructions for, in response to determining that the first cluster has exited the cluster clock gating state, increasing the supply voltage used by the processing cores of the first cluster from the second supply voltage to the first supply voltage. ### Claim 20 (depends on 16) The computer program of claim 16, wherein the first set of computer instructions determines that the first cluster of processing cores has entered the cluster clock gating state by determining (1) that all of the processing cores are in an idle, low power, state and at least one of the processing cores is in a core clock gating state or (2) that all of the processing cores are in a collapsed, low power, state and that software aggregation is being performed at a processing core level and not at a cluster level.