Photolithographic fabrication of silicon pillar arrays with perforated top electrode for trace vapor
AssigneeThe Government of the United States of America, as represented by the Secretary of the Navy
InventorsDaniel Ratchford, Braden Giordano, Junghoon Yeom
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for improving the fabrication of silicon pillar arrays and porous top electrodes for trace vapor preconcentration and partial separation. In an embodiment, the silicon pillar arrays are fabricated using photolithography or maskless photolithography combined with a dry etching process. Importantly, this process is more reproducible and scalable than the past fabrication method and yields better device performance.
Claims20
A method for photolithographic fabrication of a silicon pillar array, the method comprising:
- photolithographically defining a plurality of pillars on a silicon substrate;
- etching the silicon pillars;
- backfilling an area around the pillars with photoresist to a height just below the tops of the pillars;
- depositing, at a predetermined angle, metal on top of the photoresist, wherein each pillar in the plurality of pillars acts as a mask for a respective pore in a plurality of pores when the metal is deposited at the predetermined angle, thereby creating the plurality of pores;
- and
- removing the photoresist.
A silicon pillar array, comprising:
- a silicon substrate, comprising:
- a low resistivity substrate, and
- a high resistivity intrinsic layer on top of the low resistivity substrate;
- a plurality of pillars extending upwards from the silicon substrate;
- and
- a metal layer on top of the plurality of pillars, wherein the metal layer has a plurality of pores, and wherein each pore in the plurality of pores is positioned next to a respective pillar in the plurality of pillars.
A method for photolithographic fabrication of a silicon pillar array, the method comprising:
- photolithographically defining a plurality of pillars on a silicon substrate, wherein the silicon substrate comprises:
- a low resistivity substrate,
- a high resistivity intrinsic layer on top of the low resistivity substrate, and
- a low resistivity top epitaxial layer on top of the high resistivity intrinsic layer;
- etching the silicon pillars past the high resistivity intrinsic layer such that the high resistivity intrinsic layer forms respective cores of respective pillars in the plurality of pillars;
- backfilling an area around the pillars with photoresist to a height just below the tops of the pillars;
- depositing, at a predetermined angle, metal on top of the photoresist, wherein each pillar in the plurality of pillars acts as a mask for a respective pore in a plurality of pores when the metal is deposited at the predetermined angle, thereby creating the plurality of pores;
- and
- removing the photoresist.
Dependencies are inferred from the claim text.