Semiconductor package

A semiconductor package, comprising:

• a package substrate including a first surface and a second surface, which are opposite to each other, the package substrate comprising a first substrate pad on the first surface and a second substrate pad on the second surface;
• a first semiconductor chip on the first surface, the first semiconductor chip comprising a first chip pad;
• a connection terminal between the first substrate pad and the first chip pad;
• a second semiconductor chip on the second surface, the second semiconductor chip comprising a second chip pad on a bottom surface thereof;
• a third semiconductor chip spaced apart from the package substrate with the second semiconductor chip interposed therebetween, the third semiconductor chip comprising a third chip pad on a bottom surface thereof;
• and
• a conductive pattern electrically connecting the second substrate pad, the second chip pad, and the third chip pad to each other,
• wherein the conductive pattern is in contact with the bottom surface of the second semiconductor chip and the bottom surface of the third semiconductor chip.

A semiconductor package, comprising:

• a package substrate including a first surface and a second surface, which are opposite to each other, the package substrate comprising a first substrate pad on the first surface and a second substrate pad and a third substrate pad on the second surface;
• a first semiconductor chip on the first surface, the first semiconductor chip comprising a first chip pad;
• a connection terminal between the first substrate pad and the first chip pad;
• a first mold layer on the first surface of the package substrate and top and side surfaces of the first semiconductor chip;
• a second semiconductor chip on the second surface of the package substrate, the second semiconductor chip comprising a second chip pad;
• a third semiconductor chip spaced apart from the package substrate with the second semiconductor chip interposed therebetween, the third semiconductor chip comprising a third chip pad;
• a first adhesive layer between the second surface and the second semiconductor chip;
• a second adhesive layer between the second semiconductor chip and the third semiconductor chip;
• a second mold layer on the second surface, a bottom surface of the second semiconductor chip, and bottom and side surfaces of the third semiconductor chip;
• a conductive pattern electrically connecting the second chip pad, the third chip pad, and the second substrate pad to each other;
• a vertical conductive pillar provided on the third substrate pad to penetrate the second mold layer in a vertical direction;
• and
• an outer connection terminal on the vertical conductive pillar,
• wherein the conductive pattern has a line shape extending in a direction parallel to the first surface, on the bottom surface of the second semiconductor chip.