Radiation hardened memory cell

A memory cell comprising:

• a first n-type metal oxide semiconductor (NMOS) transistor and a first p-type metal oxide semiconductor (PMOS) transistor electrically connected to one another to form a first inverter;
• a second NMOS transistor and a second PMOS transistor electrically connected to one another to form a second inverter, the first inverter and the second inverter electrically connected to one another to form cross-coupled inverters, wherein an input of the first inverter is coupled to an output of the second inverter and an output of the first inverter is coupled to an input of the second inverter;
• a first voltage-controlled impedance component electrically connected between the output of the second inverter and a gate of the first NMOS transistor;
• a second voltage-controlled impedance component electrically connected between the output of the first inverter and a gate of the first PMOS transistor;
• a third voltage-controlled impedance component electrically connected between the output of the second inverter and a gate of the second NMOS transistor;
• and
• a fourth voltage-controlled impedance component electrically connected between the output of the first inverter and a gate of the second PMOS transistor,
• wherein an impedance of each voltage-controlled impedance component varies according to one of a plurality of control voltages applied to the respective voltage-controlled impedance component.

A memory cell comprising:

• a first n-type metal oxide semiconductor (NMOS) transistor and a second NMOS transistor electrically connected in series with one another, the first NMOS transistor and the second NMOS transistor in combination forming a first pair of NMOS transistors;
• a first p-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor electrically connected in series with one another, the first PMOS transistor and the second PMOS transistor in combination forming a first pair of PMOS transistors, the first pair of NMOS transistors and the first pair of PMOS transistors electrically connected to one another to form a first inverter;
• a third NMOS transistor and a fourth NMOS transistor electrically connected in series with one another, the third NMOS transistor and the fourth NMOS transistor in combination forming a second pair of NMOS transistors;
• a third PMOS transistor and a fourth PMOS transistor electrically connected in series with one another, the third PMOS transistor and the fourth PMOS transistor in combination forming a second pair of PMOS transistors, the second pair of NMOS transistors and the second pair of PMOS transistors electrically connected to one another to form a second inverter, the first inverter and the second inverter electrically connected to one another to form cross-coupled inverters, wherein an input of the first inverter is coupled to an output of the second inverter and an output of the first inverter is coupled to an input of the second inverter;
• a first voltage-controlled impedance component electrically connected between the output of the second inverter and first and second gates of the first pair of NMOS transistors;
• a second voltage-controlled impedance component electrically connected between the output of the second inverter and first and second gates of the first pair of NMOS transistors;
• a third voltage-controlled impedance component electrically connected between the output of the first inverter and first and second gates of the second pair of PMOS transistors;
• and
• a fourth voltage-controlled impedance component electrically connected between the output of the first inverter and first and second gates of the second pair of PMOS transistors,
• wherein an impedance of each voltage-controlled impedance component varies according to one or more of a plurality of control voltages applied to the respective voltage-controlled impedance component.