US 2026/0081592 A1Published application

Multi-stage adaptive gate drive control

AssigneeAlpha and Omega Semiconductor International LP

InventorsZiwei Yu, Lin Chen, Jian Yin

Life of this patent

Estimating the term…

Loading patent…

Abstract

Apparatus and associated methods relate to a gate drive timing controller (GDTC). In an illustrative example, the GDTC may generate a power stage activation signal (PSAS) to control an output current of a MOSFET(s) of the power stage. Three pullup transistors, for example, may be electrically connected to the control output in parallel, configured to generate the PSAS as a function of a switch node voltage (Vsw) and a source inductance voltage (VLS) of the MOSFET. For example, a first pullup transistor may be activated when a PWM signal for the power stage is received, and deactivated based on the VLS. For example, a second pullup transistor may be synchronized with the PWM signal. For example, a third pullup transistor may be activated when the Vsw is detected. Various embodiments may advantageously generate the PSAS adaptively to reduce turn-on loss of the MOSFET while keeping a low transient voltage spike.

Claims20

Dependent claims

A gate drive timing control unit comprising:

a control output operably coupled to a gate terminal of a power metal-oxide-semiconductor field-effect transistor (power MOSFET), and is configured to generate a power stage activation signal to control a power stage of the gate drive timing control unit, wherein the power stage activation signal is configured to control an output current of the power MOSFET to a load;
a sense circuit coupled to the power MOSFET configured to measure a switch node voltage and a source inductance voltage of the power MOSFET;
and,
at least three pullup transistors electrically connected to the control output in parallel, and are configured to generate the power stage activation signal as a function of the switch node voltage and the source inductance voltage, wherein:
a first pullup transistor of the at least three pullup transistors is configured to be activated when a PWM signal is received, and deactivated based on the source inductance voltage;
a second pullup transistor of the at least three pullup transistors is configured to be synchronized with the PWM signal;
and,
a third pullup transistor of the at least three pullup transistors is configured to be activated when the switch node voltage is detected.

5 more elements

A gate drive timing control unit comprising:

a control output operably coupled to a gate terminal of a power metal-oxide-semiconductor field-effect transistor (power MOSFET), and is configured to generate a power stage activation signal to control a power stage of the gate drive timing control unit, wherein the power stage activation signal is configured to control an output current of the power MOSFET to a load;
a sense circuit coupled to the power MOSFET configured to measure a switch node voltage and a source inductance voltage of the power MOSFET;
and,
an auto-adaptive control circuit configured to generate the power stage activation signal as a function of the switch node voltage and the source inductance voltage comprising:
a first stage triggered by a pulse width modulation signal (PWM signal) and ended by a detection of the source inductance voltage;
a second stage synchronized with the PWM signal;
and,
a third stage triggered by a detection of the switch node voltage, such that the power stage activation signal is adaptively generated as a function of load conditions.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/887,209Filed 17 Sep 2024
Published: 19 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 17/162
In field-effect transistor switches: without feedback from the output circuit to the control circuit
H03K 17/167
Soft switching: using parallel switching arrangements
H03K 2217/0063
Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00: high side switches, i.e.…
H03K 2217/0072
Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00: low side switches, i.e.…