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US 2026/0081585 A1Published application
Robust single event upset (seu) tolerant high-performance flip-flop
AssigneeXilinx, Inc.
InventorsTabrez ALAM, Kumar RAHUL, Santosh YACHARENI, Ishtiaque AHMAD
Life of this patent
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Abstract
Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.
Claims20
An integrated circuit, comprising:
- a master-slave latch circuit comprising master latch circuitry, slave latch circuitry, and a first tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry;
- wherein the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.
An integrated circuit, comprising:
- a master-slave latch circuit comprising master latch circuitry, slave latch circuitry, and a first tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry;
- wherein the first tristate driver comprises,
- a first inverter circuit configured to invert the output of the master latch circuitry,
- a first pull-up transistor configured to provide a supply voltage to the first inverter circuit based on a first clock, and
- a first pull-down transistor configured to provide a reference voltage to the first inverter circuit based on an inverse of the first clock.
2 more elements
An integrated circuit device, comprising:
- a field-programmable gate array (FPGA), comprising random access memory (RAM) circuitry, wherein the RAM circuitry comprises a dual double interlocked storage cell (DICE), and wherein the DICE comprises master latch circuitry, slave latch circuitry, and a first tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry;
- wherein the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.
Dependencies are inferred from the claim text.