Semiconductor memory device
OwnerTomonori KUROSAWA, Mitsuhiro ABE +1inventors
InventorsTomonori KUROSAWA, Mitsuhiro ABE, Takeshi OGAWA
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Abstract
According to one embodiment, a semiconductor memory device includes an input and output pad group, a memory cell array including a plurality of memory cells, and an input and output circuit provided between the input and output pad group and the memory cell array. The input and output circuit includes a plurality of transistors, and a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors.
Claims20
A semiconductor memory device comprising:
- an input and output pad;
- a memory cell array including a plurality of memory cells;
- and
- an input and output circuit provided between the input and output pad and the memory cell array, and including:
- a plurality of transistors;
- and
- a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors.
A semiconductor memory device comprising:
- an input and output pad;
- a memory cell array including a plurality of memory cells;
- and
- an input and output circuit provided between the input and output pad and the memory cell array, and including:
- a plurality of CMOS circuits connected in series, each including a P-channel MOSFET and an N-channel MOSFET, wherein a source of the P-channel MOSFET and a drain of the N-channel MOSFET are connected to each other;
- a first substrate bias voltage supply line through which a first substrate bias voltage is supplied to the P-channel MOSFETs;
- a second substrate bias voltage supply line through which a second substrate bias voltage is supplied to the N-channel MOSFETs;
- a first switch that connects either a first power supply line that is at a first voltage or a second power supply line that is at a second voltage that is greater than the first voltage, to the first substrate bias voltage supply line;
- and
- a second switch that connects either a third power supply line that is at a third voltage or a fourth power supply line that is at a fourth voltage that is less than the third voltage, to the second substrate bias voltage supply line.
A method of selecting a data transmission rate in a semiconductor memory device comprising an input and output pad, a memory cell array including a plurality of memory cells, and an input and output circuit provided between the input and output pad and the memory cell array, wherein
- the input and output circuit includes a plurality of transistors, and a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors, and
- said method comprises:
- controlling the substrate bias voltage supply circuit to supply the first voltage as the substrate bias voltage to select a lower data transmission rate and operate the semiconductor memory device in a power-savings mode;
- and
- controlling the substrate bias voltage supply circuit to supply the second voltage as the substrate bias voltage to select a higher data transmission rate and operate the semiconductor memory device in a high-performance mode.
Dependencies are inferred from the claim text.