Returning a contention indicator with a fetch request to allow an interrupted operation to complete
AssigneeInternational Business Machines Corporation
InventorsAshraf ElSharif, Jason D. Kohl, Gregory William Alexander
Life of this patent
Estimating the term…
Abstract
Provided are a computer implemented method, system, and computer program product for returning a contention indicator with a fetch request to allow an interrupted operation to complete. A first processor core performs an operation on a cache line. The processor core aborts the operation on the cache line in response to a fetch request for the cache line from a second processor core. The first processor core transmits a response to the fetch request including a contention indicator to cause delay of submission of an additional fetch request for the cache line.
Claims20
A computer implemented method for managing cache lines in caches for processor cores, comprising:
- performing, by a first processor core, an operation on a cache line;
- aborting, by the first processor core, the operation on the cache line in response to a fetch request for the cache line from a second processor core;
- and
- transmitting, by the first processor core, a response to the fetch request including a contention indicator to cause delay of submission of an additional fetch request for the cache line.
A system for managing cache lines in caches for processor cores, comprising:
- a first processor core;
- a second processor core,
- wherein the first processor core performs operations, the operations comprising:
- performing an operation on a cache line;
- aborting the operation on the cache line in response to a fetch request for the cache line from a second processor core;
- and
- transmitting a response to the fetch request including a contention indicator to cause delay of submission of an additional fetch request for the cache line.
A computer program product for managing cache lines in caches for processor cores, comprising a computer readable storage medium including program instructions that when executed by the processor cores perform operations, the operations comprising:
- performing, by a first processor core, an operation on a cache line;
- aborting, by the first processor core, the operation on the cache line in response to a fetch request for the cache line from a second processor core;
- and
- transmitting, by the first processor core, a response to the fetch request including a contention indicator to cause delay of submission of an additional fetch request for the cache line.
Dependencies are inferred from the claim text.