Apparatus and Method for Prefetching from a Second Level Translation Lookaside Buffer (TLB) to a First Level TLB

A method, comprising:

• fetching, by front end circuitry of a processor, a plurality of instructions from a memory;
• executing, by out-of-order execution circuitry, the plurality of instructions, wherein a subset of the plurality of instructions are to cause memory access operations;
• performing a lookup in a first level (L1) translation lookaside buffer (TLB) coupled to or integral to the out-of-order execution circuitry to attempt to locate first virtual to physical address translations;
• performing a lookup in a second level translation lookaside buffer (STLB) coupled to or integral to the out-of-order execution circuitry in response to a miss at the L1 TLB;
• and
• prefetching, by prefetch circuitry, a first entry from the STLB into the L1 TLB, the prefetch circuitry to perform additional prefetches in accordance with a selected operational mode, wherein in a first operational mode, a plurality of sequential entries are to be prefetched from the STLB following the first entry and, in a second operational mode, a plurality of entries indicated in a temporal pattern table entry corresponding to the first entry are to be prefetched.

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations, comprising:

• fetching, by front end circuitry of a processor, a plurality of instructions from a memory;
• executing, by out-of-order execution circuitry, the plurality of instructions, wherein a subset of the plurality of instructions are to cause memory access operations;
• performing a lookup in a first level (L1) translation lookaside buffer (TLB) coupled to or integral to the out-of-order execution circuitry to attempt to locate first virtual to physical address translations;
• performing a lookup in a second level translation lookaside buffer (STLB) coupled to or integral to the out-of-order execution circuitry in response to a miss at the L1 TLB;
• and
• prefetching, by prefetch circuitry, a first entry from the STLB into the L1 TLB, the prefetch circuitry to perform additional prefetches in accordance with a selected operational mode, wherein in a first operational mode, a plurality of sequential entries are to be prefetched from the STLB following the first entry and, in a second operational mode, a plurality of entries indicated in a temporal pattern table entry corresponding to the first entry are to be prefetched.