Analog divider circuitry with built-in test capability
AssigneeSkyworks Solutions, Inc.
InventorsKalyana Chakravarthy Vullaganti, James David Barnette, Sanjeev Tannirkulam Chandrasekaran, Raghunandan Kolar Ranganathan
Life of this patent
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Abstract
A divider circuit includes an analog divider circuit with pre-load circuitry configured to allow for a programmable starting value. The circuit is responsive, synchronous with a divider clock, to count from the starting value, and includes an observation bus that outputs a current count value of the analog divider circuit. The divider circuit further includes test clock logic configured, in a divider circuit test mode, to be responsive to a reference clock to output the divider clock to clock the analog divider circuit for a number of clock cycles corresponding to a programmable test clock length.
Claims20
A timing circuit comprising:
- an analog divider circuit including pre-load circuitry configured to allow for programming the analog divider circuit with a starting value, and responsive, synchronous with a divider clock, to count from the starting value, and the analog divider circuit further including an observation bus that outputs a current count value of the analog divider circuit;
- and
- test clock logic configured, in a divider circuit test mode, to be responsive to a reference clock to output the divider clock to clock the analog divider circuit for a number of clock cycles corresponding to a programmable test clock length.
A timing system comprising:
- at least one timing circuit having a first divider circuit including pre-load circuitry configured to allow for programming the first divider circuit with a starting value, and the first divider circuit responsive, synchronous with a divider clock, to count from the starting value, and the first divider circuit further including an observation bus that outputs a current count value of the first divider circuit, the at least one timing circuit further including test clock logic configured, in a divider circuit test mode, to be responsive to a reference clock to output the divider clock to clock the first divider circuit for a number of clock cycles corresponding to a programmable test clock length.
A method of operating a timing circuit comprising:
- programming an analog divider circuit of the timing circuit with a starting value using pre-load circuitry of the analog divider circuit;
- counting, synchronous with a divider clock, from the starting value;
- outputting with an observation bus of the analog divider circuit, a current count value of the analog divider circuit;
- and
- with test clock logic of the timing circuit, in a divider circuit test mode and responsive to a reference clock, outputting the divider clock to clock the analog divider circuit for a number of clock cycles corresponding to a programmable test clock length.
Dependencies are inferred from the claim text.