# US 2026/0076271 A1 · Electronic package having stepped stacked substrate structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076271 A1 - Document ID: US20260076271A1 - Status: Published application - Kind: A1 - Application number: 18/883,570 - Filed: 2024-09-12 - Published: 2026-03-12 - Earliest claimed: 2024-09-12 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Manuel ALDRETE; Aniket PATIL; Rajneesh KUMAR; Piyush GUPTA - Web page: https://patentgrep.com/patent/US20260076271A1 ## CPC - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/685: comprising multiple insulating layers - H10W 72/30: Die-attach connectors - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract In an aspect, an electronic device includes a plurality of stacked substrates, each substrate includes a first planar surface and a second planar surface opposite the first planar surface. Adjacent substrates are stacked so that the second planar surface of each upper substrate of the adjacent substrates extends beyond the first planar surface of each lower substrate of the adjacent substrates to form planar connection surfaces at the second planar surface of the upper substrate of the adjacent substrates, A redistribution layer underlies the stacked substrates. Conductive pillars extend in a direction perpendicular to the planar connection surface of each upper substrate of the adjacent substrates to electrically connect the electronic components of each upper substrate to the redistribution layer. ## Claims ### Claim 1 An electronic device, comprising: a plurality of stacked substrates, each substrate including a first planar surface, a second planar surface opposite the first planar surface, wherein adjacent substrates of the plurality of stacked substrates are stacked so that the second planar surface of each upper substrate of the adjacent substrates extends beyond the first planar surface of each lower substrate of the adjacent substrates to form planar connection surfaces at the second planar surface of the upper substrate of the adjacent substrates; a redistribution layer underlying the plurality of stacked substrates; and one or more conductive pillars extending from the planar connection surface of each upper substrate of the adjacent substrates to electrically connect one or more electronic components of each upper substrate to the redistribution layer, wherein the one or more conductive pillars extend perpendicularly from the planar connection surfaces of each upper substrate to the redistribution layer. ### Claim 2 (depends on 1) The electronic device of claim 1, further comprising: an over-molding material at least partially surrounding the plurality of stacked substrates and the one or more conductive pillars. ### Claim 3 (depends on 1) The electronic device of claim 1, wherein: at least one of the substrates of the plurality of stacked substrates comprises a memory substrate. ### Claim 4 (depends on 1) The electronic device of claim 1, wherein: at least one of the substrates of the plurality of substrates comprises a passive component substrate. ### Claim 5 (depends on 1) The electronic device of claim 1, further comprising: a further substrate having a first planar surface and a second planar surface opposite the first planar surface, wherein the first planar surface of the further substrate is disposed adjacent the second planar surface of a lowermost substrate of the plurality of stacked substrates. ### Claim 6 (depends on 5) The electronic device of claim 5, wherein: the further substrate comprises a flip chip processor. ### Claim 7 (depends on 1) The electronic device of claim 1, wherein: the first planar surface of each lower substrate of the adjacent substrates extends beyond the second planar surface of each upper substrate of the adjacent substrates to form thermal dissipation surfaces at the first planar surface of the lower substrate of the adjacent substrates; and the electronic device further comprising one or more metal slugs overlying one or more of the thermal dissipation surfaces. ### Claim 8 (depends on 1) The electronic device of claim 1, wherein the electronic device comprises at least one of: a music player; a video player; an entertainment unit; a navigation device; a communications device; a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed location terminal; a tablet computer, a computer; a wearable device; a laptop computer; a server; an internet of things (IoT) device; or a device in an automotive vehicle. ### Claim 9 A stacked substrate structure, comprising: a plurality of stacked substrates, each substrate including a first planar surface, a second planar surface opposite the first planar surface, wherein adjacent substrates of the plurality of stacked substrates are stacked so that the second planar surface of each upper substrate of the adjacent substrates extends beyond the first planar surface of each lower substrate of the adjacent substrates to form planar connection surfaces at the second planar surface of the upper substrate of the adjacent substrates; a redistribution layer overlying the plurality of stacked substrates; and one or more conductive pillars extending from the planar connection surface of each upper substrate of the adjacent substrates to electrically connect one or more electronic components of each upper substrate to the redistribution layer, wherein the one or more conductive pillars extend perpendicularly from the planar connection surfaces of each upper substrate to the redistribution layer. ### Claim 10 (depends on 9) The stacked substrate structure of claim 9, further comprising: an over-molding material at least partially surrounding the plurality of stacked substrates and the one or more conductive pillars. ### Claim 11 (depends on 9) The stacked substrate structure of claim 9, wherein: at least one of the substrates of the plurality of stacked substrates comprises a memory substrate. ### Claim 12 (depends on 9) The stacked substrate structure of claim 9, wherein: at least one of the substrates of the plurality of substrates comprises a passive component substrate. ### Claim 13 (depends on 9) The stacked substrate structure of claim 9, further comprising: a further substrate having a first planar surface and a second planar surface opposite the first planar surface, wherein the first planar surface of the further substrate is disposed adjacent the second planar surface of a lowermost substrate of the plurality of stacked substrates. ### Claim 14 (depends on 13) The stacked substrate structure of claim 13, wherein: the further substrate comprises a flip chip processor. ### Claim 15 (depends on 9) The stacked substrate structure of claim 9, wherein: the first planar surface of each lower substrate of the adjacent substrates extends beyond the second planar surface of each upper substrate of the adjacent substrates to form thermal dissipation surfaces at the first planar surface of the lower substrate of the adjacent substrates; and the stacked substrate structure further comprising one or more metal slugs overlying one or more of the thermal dissipation surfaces. ### Claim 16 A method of forming stacked substrate structure, comprising: stacking a plurality of substrates, each substrate including a first planar surface, a second planar surface opposite the first planar surface, wherein adjacent substrates of the plurality of stacked substrates are stacked so that the second planar surface of each upper substrate of the adjacent substrates extends beyond the first planar surface of each lower substrate of the adjacent substrates to form planar connection surfaces at the second planar surface of the upper substrate of the adjacent substrates; forming a redistribution layer overlying the plurality of substrates; and forming one or more conductive pillars extending from the planar connection surface of each upper substrate of the adjacent substrates to electrically connect one or more electronic components of each upper substrate to the redistribution layer, wherein the one or more conductive pillars extend perpendicularly from the planar connection surfaces of each upper substrate to the redistribution layer. ### Claim 17 (depends on 16) The method of claim 16, further comprising: performing an over-molding operation to at least partially surround the plurality of stacked substrates and the one or more conductive pillars with an over-molding material. ### Claim 18 (depends on 16) The method of claim 16, wherein: at least one of the substrates of the plurality of stacked substrates comprises a memory substrate. ### Claim 19 (depends on 16) The method of claim 16, further comprising: attaching a flip chip processor having a first planar surface and a second planar surface opposite the first planar surface so that the first planar surface of the flip chip processor is disposed adjacent the second planar surface of a lowermost substrate of the plurality of substrates. ### Claim 20 (depends on 16) The method of claim 16, wherein: the first planar surface of each lower substrate of the adjacent substrates extends beyond the second planar surface of each upper substrate of the adjacent substrates to form thermal dissipation surfaces at the first planar surface of the lower substrate of the adjacent substrates; and the method further comprising: forming one or more metal slugs over the one or more of the thermal dissipation surfaces.