# US 2026/0076265 A1 · Communication protocol using free-space connectivity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076265 A1 - Document ID: US20260076265A1 - Status: Published application - Kind: A1 - Application number: 19/389,065 - Filed: 2025-11-14 - Published: 2026-03-12 - Earliest claimed: 2025-06-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Shamsul ABEDIN; Dekang CHEN; Stephen MOREIN; Tina C. TOUPAL; Zhen ZHOU - Web page: https://patentgrep.com/patent/US20260076265A1 ## CPC - H10W 90/00: Package configurations - H10W 72/90: Bond pads, in general - H10W 90/20: Configurations of stacked chips - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A device may include a first die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to generate a transmission asynchronous pattern; receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die; control a data transfer between the first die and the second die via the data transmission interface based on the response pattern; and a second die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to receive the transmission asynchronous pattern; check whether the received transmission asynchronous pattern is correct; generate a response pattern indicating whether the received transmission asynchronous pattern is correct; control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous pattern is correct. ## Claims ### Claim 1 A device comprising: a plurality of chiplets stacked on top of each other, wherein each chiplet comprises: one or more electronic components; a plurality of connections electrically connecting the one or more electronic components, the plurality of connections formed in one or more metal layers; and main surfaces and side surfaces, wherein the main surfaces of adjacent chiplets of the plurality of chiplets face each other; a carrier comprising a processor; a first transmitter electrically coupled to one or more chiplets of the plurality of chiplets; a first receiver coupled to the first transmitter and electrically coupled to the processor; a second transmitter electrically coupled to the processor; and a second receiver coupled to the second transmitter and electrically coupled to one or more chiplets of the plurality of chiplets. ### Claim 2 (depends on 1) The device of claim 1, wherein the first transmitter is a first optical transmitter electrically coupled to one or more chiplets of the plurality of chiplets, wherein the first receiver is a first optical receiver optically coupled to the first optical transmitter and electrically coupled to the processor, wherein the second transmitter is a second optical transmitter electrically coupled to the processor, wherein the second receiver is a second optical receiver optically coupled to the second optical transmitter and electrically coupled to one or more chiplets of the plurality of chiplets. ### Claim 3 (depends on 2) The device of claim 2, wherein the first transmitter is a first inductive transmitter electrically coupled to one or more chiplets of the plurality of chiplets, wherein the first receiver is a first inductive receiver inductively coupled to the first inductive transmitter and electrically coupled to the processor, wherein the second transmitter is a second inductive transmitter electrically coupled to the processor, wherein the second receiver is a second inductive receiver inductively coupled to the second optical transmitter and electrically coupled to one or more chiplets of the plurality of chiplets. ### Claim 4 (depends on 1) The device of claim 1, wherein the first transmitter is a first capacitive transmitter electrically coupled to one or more chiplets of the plurality of chiplets, wherein the first receiver is a first capacitive receiver capacitively coupled to the first capacitive transmitter and electrically coupled to the processor, wherein the second transmitter is a second capacitive transmitter electrically coupled to the processor, wherein the second receiver is a second capacitive receiver capacitively coupled to the second capacitive transmitter and electrically coupled to one or more chiplets of the plurality of chiplets. ### Claim 5 (depends on 1) The device of claim 1, the device further comprising a package substrate positioned between the plurality of chiplets and the carrier, wherein the first receiver is coupled to the first transmitter via the package substrate, and/or wherein the second receiver is coupled to the second transmitter via the package substrate. ### Claim 6 (depends on 1) The device of claim 1, wherein the first receiver is coupled to the first transmitter via a first transmission path that is transparent for signals transmitted by the first transmitter and/or wherein the second receiver is coupled to the second transmitter via a second transmission path that is transparent for signals transmitted by the second transmitter. ### Claim 7 (depends on 6) The device of claim 6, the device further comprising a package substrate positioned between the plurality of chiplets and the carrier, wherein the package substrate comprises material in a region of the first transmission path and/or the second transmission path that is transparent for signals transmitted by the first transmitter and/or the second transmitter. ### Claim 8 (depends on 1) The device of claim 1, the device further comprising one or more first optical elements optically coupled to an output of the first transmitter and/or wherein one or more second optical elements optically coupled to an output of the second transmitter. ### Claim 9 (depends on 8) The device of claim 8, wherein the one or more first optical elements comprise one or more first lenses and/or wherein one or more second optical elements comprise one or more second lenses. ### Claim 10 (depends on 8) The device of claim 8, wherein the one or more first optical elements are configured as a collimator or as a focus element and/or wherein one or more second optical elements are configured as a collimator or as a focus element. ### Claim 11 (depends on 8) The device of claim 8, wherein the first receiver is coupled to the first transmitter via a first transmission path that is transparent for signals transmitted by the first transmitter and/or wherein the second receiver is coupled to the second transmitter via a second transmission path that is transparent for signals transmitted by the second transmitter, and wherein the one or more first optical elements are configured to be adjustable with respect to the first transmission path and/or wherein the one or more second optical elements are configured to be adjustable with respect to the second transmission path. ### Claim 12 (depends on 11) The device of claim 11, wherein the first transmitter comprises a plurality of first transmitter elements, wherein the first receiver comprises a plurality of first receiver elements, the device further comprising a selector configured to select at least one pair of a first transmitter from the plurality of first transmitters and a first receiver from the plurality of first receivers to provide the first transmission path. ### Claim 13 (depends on 11) The device of claim 11, wherein the second transmitter comprises a plurality of second transmitter elements, wherein the second receiver comprises a plurality of second receiver elements, the device further comprising a selector configured to select at least one pair of a second transmitter from the plurality of second transmitters and a second receiver from the plurality of second receivers to provide the second transmission path. ### Claim 14 A device comprising: a first die and a second die, the first die comprising a data transmission interface configured to transmit and receive signals and a processor configured to: generate a transmission asynchronous pattern; receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die; and control a data transfer between the first die and the second die via the data transmission interface based on the response pattern, the second die comprising: a data transmission interface configured to transmit and receive signals and a processor configured to: receive the transmission asynchronous pattern; check whether the received transmission asynchronous pattern is correct; generate a response pattern indicating whether the received transmission asynchronous pattern is correct; and control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous pattern is correct. ### Claim 15 (depends on 14) The device of claim 14, wherein the data transmission interface of the first die and/or of the second die is configured to inductively, capacitively, or optically transmit and receive signals and/or wherein the data transmission interface of the second die is configured to inductively transmit and receive signals. ### Claim 16 (depends on 14) The device of claim 14, wherein the data transmission interface of the first die comprises one or more transmit analog front end circuits configured to transmit signals and/or wherein the data transmission interface of the first die comprises one or more receive analog front end circuits configured to receive signals. ### Claim 17 (depends on 14) The device of claim 14, wherein the data transmission interface of the second die comprises one or more transmit analog front end circuits configured to transmit signals and/or wherein the data transmission interface of the second die comprises one or more receive analog front end circuits configured to receive signals. ### Claim 18 (depends on 14) The device of claim 14, wherein the processor of the first die comprises: an asynchronous pattern generator; a response pattern checker; and an initialization controller configured to control the asynchronous pattern generator. ### Claim 19 A device comprising: a first die and a second die, the first die comprising: an encoder comprising a plurality of encoder outputs and configured to generate bit signals on the encoder outputs of the plurality of encoder outputs; a plurality of transmit analog front end circuits configured to transmit signals, each transmit analog front end circuit coupled to an encoder output of the plurality of encoder outputs, wherein the encoder is configured to: in a first time period provided for first bit signals, provide a first bit signal of a first bit signal level representing a first bit value or a first bit signal of a second bit signal level representing a second bit value only on some encoder outputs of the plurality of encoder outputs; and in a second time period provided for second bit signals, the second time period immediately following the first time period, provide a second bit signal of a first bit signal level representing a first bit value or a second bit signal of a second bit signal level representing a second bit value only on some encoder outputs of the plurality of encoder outputs in which no first bit signals have been provided in the first time period, wherein the second die comprises: a plurality of receive analog front end circuits configured to receive signals, each receive analog front end circuit inductively coupled with an associated transmit analog front end circuit of the first die; and a decoder comprising a plurality of decoder inputs and a plurality of decoder outputs, wherein each decoder input is coupled to an associated receive analog front end circuit of the plurality of receive analog front end circuits, wherein the decoder is configured to generate bit signals on the decoder outputs based on the signals received on the decoder inputs. ### Claim 20 (depends on 19) The device of claim 19, wherein the encoder comprises multiple encoders, each of which are associated with one of different transmit sets of the plurality of transmit analog front end circuits, wherein the decoder comprises multiple decoders, each of which are associated with one of different receive sets of the plurality of receive analog front end circuits, wherein each corresponding one of the different transmit sets corresponds to a corresponding receive set of the different receive sets, wherein each corresponding one of the different transmit sets and its corresponding one set of the different receive sets.