# US 2026/0076264 A1 · Multi-reticle device with electrical and optical stitching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076264 A1 - Document ID: US20260076264A1 - Status: Published application - Kind: A1 - Application number: 19/323,149 - Filed: 2025-09-09 - Published: 2026-03-12 - Earliest claimed: 2024-09-10 - Assignees: Lightmatter, Inc. - Applicants: Lightmatter, Inc. - Inventors: Mitul Modi; Anandaroop Ghosh; Tushar Dinkar Wakharkar; Daniel Stodolsky; Sandeep Sane; Nikhil Kumar - Web page: https://patentgrep.com/patent/US20260076264A1 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H10W 90/00: Package configurations - G03F 7/70475: {Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 70/616: {package substrates, interposers or redistribution layers combined with bridge chips} - H10W 70/635: {Through-vias} - H10W 90/295: {optical coupling} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract Hybrid interconnect schemes that combine both electrical and optical stitching are described. Electrical stitching is well-suited for short-reach, high-bandwidth connections between adjacent or closely spaced units. On the other hand, optical stitching is well-suited for long-reach, low-loss connections between non-adjacent units. By leveraging the complementary nature of electrical and optical stitching, a multi-reticle device may be constructed that provides substantially greater scalability in terms of compute and memory density and overall interconnect bandwidth than is achievable using conventional approaches. An intermediate connection layer is configured to electrically connect electrical integrated circuits (EIC) of the plurality of EICs that are within a cutoff range of one another. An electro-optical interposer is configured to optically connect EICs of the plurality of EICs that are outside the cutoff range of one another. ## Claims ### Claim 1 A multi-reticle device comprising: an intermediate connection layer comprising a top side and a bottom side; a plurality of electrical integrated circuits (EICs) coupled to the top side of the intermediate connection layer; and an electro-optical interposer coupled to the bottom side of the intermediate connection layer, the electro-optical interposer comprising a plurality of tiles, wherein each tile comprises an electrical layer and an optical layer, wherein: the intermediate layer electrically connects a first EIC of the plurality of EICs to a second EIC of the plurality of EICs, wherein the first EIC is adjacent to the second EIC; and the electro-optical interposer optically connects the first EIC to a third EIC of the plurality of EICs, wherein the third EIC is not adjacent to the first EIC. ### Claim 2 (depends on 1) The multi-reticle device of claim 1, wherein the intermediate connection layer comprises a silicon bridge embedded in a mold matrix, wherein the silicon bridge electrically connects the first EIC to the second EIC. ### Claim 3 (depends on 2) The multi-reticle device of claim 2, wherein the intermediate connection layer further comprises a plurality of vertical connections embedded in the mold matrix, the plurality of vertical connections electrically connecting the first EIC to the electro-optical interposer. ### Claim 4 (depends on 1) The multi-reticle device of claim 1, wherein the intermediate connection layer comprises a silicon interposer. ### Claim 5 (depends on 1) The multi-reticle device of claim 1, wherein the intermediate connection layer comprises a redistribution layer. ### Claim 6 (depends on 1) The multi-reticle device of claim 1, further comprising a redistribution layer coupled to the electro-optical interposer such that the electro-optical interposer is between the intermediate connection layer and the redistribution layer. ### Claim 7 (depends on 1) The multi-reticle device of claim 1, wherein the plurality of EICs comprise a plurality of memory chips and at least one application specific integrated circuit (ASIC). ### Claim 8 (depends on 1) The multi-reticle device of claim 1, wherein the plurality of EICs are arranged in a plurality of unit cells, each unit cell comprising at least one ASIC and at least four memory chips. ### Claim 9 A multi-reticle device comprising: a plurality of electrical integrated circuits (EICs) arranged in a plurality of unit cells, each unit cell comprising at least one application specific integrated circuit (ASIC) and a plurality of memory chips; an intermediate connection layer comprising a top side and a bottom side, wherein the plurality of EICs are coupled to the top side of the intermediate connection layer, wherein the intermediate connection layer is configured to electrically connect an ASIC of a first unit cell of the plurality of units cells to the plurality of memory chips of the first unit cell; and an electro-optical interposer comprising a plurality of tiles, wherein the electro-optical interposer is coupled to the bottom side of the intermediate connection layer, wherein the electro-optical interposer is configured to optically connect the ASIC of the first unit cell to the plurality of memory chips of a second unit cell of the plurality of unit cells. ### Claim 10 (depends on 9) The multi-reticle device of claim 9, further comprising a plurality of vertical connections formed in the intermediate connection layer, the plurality of vertical connections electrically connecting tiles of the electro-optical interposer to unit cells in accordance with a 1-to-1 correspondence. ### Claim 11 (depends on 9) The multi-reticle device of claim 9, further comprising a plurality of vertical connections formed in the intermediate connection layer, the plurality of vertical connections electrically connecting tiles of the electro-optical interposer to unit cells in accordance with a N-to-1correspondence, where N is greater than 1. ### Claim 12 (depends on 9) The multi-reticle device of claim 9, wherein the intermediate connection layer comprises at least one selected from the group consisting of a redistribution layer, a silicon interposer and a plurality of silicon bridges. ### Claim 13 (depends on 9) The multi-reticle device of claim 9, further comprising a Universal Chiplet Interconnect Express (UCIe) interface configured to place the ASIC of the first unit cell in communication with the plurality of memory chips of the first unit cells. ### Claim 14 (depends on 9) The multi-reticle device of claim 9, further comprising a redistribution layer coupled to the electro-optical interposer such that the electro-optical interposer is between the intermediate connection layer and the redistribution layer. ### Claim 15 A multi-reticle device comprising: an intermediate connection layer comprising a top side configured to be electrically coupled to a plurality of electrical integrated circuits (EIC), wherein the intermediate connection layer is configured to electrically connect EICs of the plurality of EICs that are within a cutoff range of one another; and an electro-optical interposer co-packaged with the intermediate connection layer, wherein the electro-optical interposer is configured to optically connect EICs of the plurality of EICs that are outside the cutoff range of one another. ### Claim 16 (depends on 15) The multi-reticle device of claim 15, wherein the cutoff range is 5 mm. ### Claim 17 (depends on 15) The multi-reticle device of claim 15, wherein the cutoff range is 3 mm. ### Claim 18 (depends on 15) The multi-reticle device of claim 15, wherein the intermediate connection layer comprises at least one selected from the group consisting of a redistribution layer, a silicon interposer and a plurality of silicon bridges. ### Claim 19 (depends on 15) The multi-reticle device of claim 15, further comprising a Universal Chiplet Interconnect Express (UCIe) interface configured to place EICs that are within the cutoff range of one another in communication with one another. ### Claim 20 (depends on 15) The multi-reticle device of claim 15, further comprising a redistribution layer coupled to the electro-optical interposer such that the electro-optical interposer is between the intermediate connection layer and the redistribution layer.