# US 2026/0076261 A1 · Semiconductor structure and fabrication method thereof and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076261 A1 - Document ID: US20260076261A1 - Status: Published application - Kind: A1 - Application number: 19/236,785 - Filed: 2025-06-12 - Published: 2026-03-12 - Earliest claimed: 2024-09-10 - Assignees: Yangtze Memory Technologies Holding Co., Ltd. - Applicants: Yangtze Memory Technologies Holding Co., Ltd. - Inventors: Huijie Zhu; Peng Chen; Ping Mo; Xinru Zeng; Zhong Lv - Web page: https://patentgrep.com/patent/US20260076261A1 ## CPC - H10W 90/00: Package configurations - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Examples of the present disclosure provide a semiconductor structure and a fabrication method thereof and a semiconductor device, and relates to the field of semiconductor technology. The semiconductor structure includes a interposer layer and a bonding block that are stacked together. The bonding block includes a connection portion and a plurality of stacks, and the connection portion connects any two adjacent stacks. Any one of the stacks is bonded with the interposer layer. In the examples, the connection portion connects any two adjacent stacks, such that the plurality of stacks in the bonding block can be jointly bonded with the interposer layer, and there is no need to bond the plurality of stacks with the interposer layer separately, thereby improving production efficiency and unit per hour of the semiconductor structure and also improving convenience of bonding between the stacks and interposer layer, which facilitates miniaturization of the stacks. ## Claims ### Claim 1 A semiconductor structure, comprising: an interposer layer; and a bonding block, wherein the bonding block and the interposer layer are stacked together; the bonding block comprises a connection portion and a plurality of stacks; the connection portion connects any two adjacent ones of the plurality of stacks; and any one of the plurality of stacks is bonded with the interposer layer. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the semiconductor structure comprises a plurality of bonding blocks; the plurality of bonding blocks are stacked together; and any two adjacent ones of the plurality of bonding blocks are bonded with each other. ### Claim 3 (depends on 2) The semiconductor structure of claim 2, wherein in any two adjacent ones of the plurality of bonding blocks, a plurality of stacks in one bonding block and a plurality of stacks in the other bonding block are bonded in a one-to-one correspondence. ### Claim 4 (depends on 1) The semiconductor structure of claim 1, wherein the connection portion comprises a connection medium and metal routings embedded in the connection medium. ### Claim 5 (depends on 1) The semiconductor structure of claim 1, wherein the stack comprises a logic chip and a memory chip that are stacked together, and the memory chip is bonded with the logic chip. ### Claim 6 (depends on 5) The semiconductor structure of claim 5, wherein the stack comprises a plurality of memory chips that are stacked together on a side of the logic chip, and any two adjacent ones of the plurality of memory chips are bonded with each other. ### Claim 7 (depends on 5) The semiconductor structure of claim 5, wherein the memory chip and the logic chip are bonded by at least one of adhesive bonding, anodic bonding, direct wafer bonding, metal bonding and hybrid bonding. ### Claim 8 (depends on 1) The semiconductor structure of claim 1, wherein the bonding block and the interposer layer are bonded by at least one of adhesive bonding, anodic bonding, direct wafer bonding, metal bonding and hybrid bonding. ### Claim 9 (depends on 1) The semiconductor structure of claim 1, wherein the plurality of stacks are arranged along at least one of a first direction and a second direction, the first direction intersects the second direction, and a plane where the first direction and the second direction are located is parallel to the interposer layer. ### Claim 10 A fabrication method of a semiconductor structure, comprising: forming a bonding block that comprises a connection portion and a plurality of stacks, wherein the connection portion connects any two adjacent ones of the plurality of stacks; and bonding any one of the plurality of stacks with an interposer layer. ### Claim 11 (depends on 10) The fabrication method of the semiconductor structure of claim 10, wherein forming the bonding block comprises: bonding a memory wafer and a logic wafer to form a stack wafer comprising m stacks that are connected together; and cutting the stack wafer to form the bonding block comprising n stacks that are connected together, wherein m is greater than or equal to n, and both m and n are positive integers greater than 1. ### Claim 12 (depends on 11) The fabrication method of the semiconductor structure of claim 11, wherein m is greater than m, and after bonding the memory wafer and the logic wafer, the fabrication method comprises: cutting the stack wafer to form a first stack and a second stack. ### Claim 13 (depends on 11) The fabrication method of the semiconductor structure of claim 11, wherein before bonding the memory wafer and the logic wafer, the fabrication method further comprises: forming the memory wafer on a side of a first substrate, wherein the memory wafer comprises a plurality of memory chips, and any two adjacent ones of the plurality of memory chips are connected with each other; forming the logic wafer on a side of a second substrate, wherein the logic wafer comprises a plurality of logic chips, and any two adjacent ones of the plurality of logic chips are connected with each other; and bonding the memory wafer and the logic wafer comprises: bonding the plurality of memory chips and the plurality of logic chips in a one-to-one correspondence. ### Claim 14 A semiconductor device, comprising: a circuit board; and a semiconductor structure comprising: an interposer layer; and a bonding block, wherein the bonding block and the interposer layer are stacked together; the bonding block comprises a connection portion and a plurality of stacks; the connection portion connects any two adjacent ones of the plurality of stacks; and any one of the plurality of stacks is bonded with the interposer layer, wherein the interposer layer of the semiconductor structure is coupled with the circuit board. ### Claim 15 (depends on 14) The semiconductor device of claim 14, further comprising a die that is bonded with the interposer layer. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the die comprises a graphics processing unit. ### Claim 17 (depends on 14) The semiconductor device of claim 14, wherein the semiconductor structure comprises a plurality of bonding blocks; the plurality of bonding blocks are stacked together; and any two adjacent ones of the plurality of bonding blocks are bonded with each other. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein in any two adjacent ones of the plurality of bonding blocks, a plurality of stacks in one bonding block and a plurality of stacks in the other bonding block are bonded in a one-to-one correspondence. ### Claim 19 (depends on 14) The semiconductor device of claim 14, wherein the connection portion comprises a connection medium and metal routings embedded in the connection medium. ### Claim 20 (depends on 14) The semiconductor device of claim 14, wherein the stack comprises a logic chip and a memory chip that are stacked together, and the memory chip is bonded with the logic chip.