# US 2026/0076258 A1 · Package structures and methods of forming same

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- Number: US 2026/0076258 A1
- Document ID: US20260076258A1
- Status: Published application
- Kind: A1
- Application number: 18/989,614
- Filed: 2024-12-20
- Published: 2026-03-12
- Earliest claimed: 2024-09-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jyun-Siang Peng; Meng-Wei Chou; Yu-Hsiang Hu; Chien-Hsun Lee; Kathy Wei Yan
- Web page: https://patentgrep.com/patent/US20260076258A1

## CPC

- H10W 90/00: Package configurations
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 70/23: {during, before or after processing of insulating materials}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 40/037: {Assembling together parts thereof}
- H10W 70/611: {for connecting multiple chips together}
- H10W 74/016: {using moulds}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)}
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes providing an interposer structure including conductive paths, forming micro bumps over the interposer structure and connected to the conductive paths, bonding a first die and a second die onto the micro bumps, forming a molding compound over and around the first die and the second die, performing a planarization process to expose a top surface of the second die, forming a trench in the molding compound to expose a top surface of the first die, forming a thermal interface material (TIM) layer in the trench and over the top surface of the second die, bonding the interposer structure to a substrate, and attaching a heat sink onto the TIM layer. The first die has a first height and the second die has a second height greater than the first height.

## Claims

### Claim 1

A method, comprising:
providing an interposer structure including conductive paths;
forming micro bumps over the interposer structure and connected to the conductive paths;
bonding a first die and a second die onto the micro bumps, wherein the first die has a first height and the second die has a second height greater than the first height;
forming a molding compound over and around the first die and the second die;
performing a planarization process to expose a top surface of the second die;
forming a trench in the molding compound to expose a top surface of the first die;
forming a thermal interface material (TIM) layer in the trench and over the top surface of the second die;
bonding the interposer structure to a substrate; and
attaching a heat sink onto the TIM layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first die is a system-on-chip (SoC) die or a system-on-integrated-chips (SoIC) die, and the second die is a high bandwidth memory (HBM) die.

### Claim 3 (depends on 1)

The method of claim 1, further comprising bonding a third die onto the micro bumps,
wherein the third die has a third height smaller than the first height, and
wherein the method further comprises extending the trench to expose a top surface of the third die.

### Claim 4 (depends on 1)

The method of claim 1, further comprising performing a cleaning process before forming the TIM layer in the trench and over the top surface of the second die.

### Claim 5 (depends on 1)

The method of claim 1, before forming the TIM layer in the trench and over the top surface of the second die, further comprising forming a backside metal (BSM) layer in a bottom and a sidewall of the trench and on the top surface of the second die,
wherein the TIM layer is formed over the BSM layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the micro bumps have a same height.

### Claim 7 (depends on 1)

The method of claim 1, wherein the micro bumps include first micro bumps and second micro bumps having different heights.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first die is a high bandwidth memory (HBM) die, and the second die is a system-on-chip (SoC) die or a system-on-integrated-chips (SoIC) die.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first die and the second each include a die and a connecting structure,
wherein the connecting structure includes conductive traces, a passivation layer surrounding the conductive traces, and upper micro bumps connected to the micro bumps.

### Claim 10

A method, comprising:
providing an interposer structure including a first region and a second region;
forming first micro bumps over the first region and second micro bumps over the second region, wherein the first micro bumps have a first height and the second micro bumps have a second height greater than the first height;
bonding a first die onto the first micro bumps and a second die onto the second micro bumps;
depositing a molding compound around the first die and the second die;
bonding the interposer structure to a substrate; and
bonding a heat sink to the first die and the second die.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first die has a third height and the second die has a fourth height smaller than the third height.

### Claim 12 (depends on 10)

The method of claim 10, wherein the heat sink is bonded to the first die and the second die by a thermal interface material (TIM).

### Claim 13 (depends on 10)

The method of claim 10, wherein the interposer structure further includes a third region,
wherein the method further comprises forming third micro bumps over the third region,
wherein the third micro bumps have a third height greater than the second height,
wherein the method further comprises bonding a third die onto the third micro bumps,
wherein the molding compound is further deposited around the third die, and
wherein the heat sink is further bonded to the third die.

### Claim 14 (depends on 10)

The method of claim 10, wherein forming the first micro bumps over the first region and the second micro bumps over the second region includes:
forming a first photoresist layer over the interposer structure;
patterning the first photoresist layer to form first trenches in the first photoresist layer over the first region;
forming the first micro bumps in the first trenches;
removing the first photoresist layer;
forming a second photoresist layer over the interposer structure and the first micro bumps;
patterning the second photoresist layer to form second trenches in the second photoresist layer over the second region;
forming the second micro bumps in the second trenches; and
removing the second photoresist layer.

### Claim 15 (depends on 10)

The method of claim 10, wherein top surfaces of the first die and the second die are coplanar.

### Claim 16 (depends on 10)

The method of claim 10, wherein depositing the molding compound further deposits the molding compound over a top surface of the first die and a top surface of the second die;
wherein the top surface of the first die is higher than the top surface of the second die; and
after depositing the molding compound, the method further comprises:
performing a planarization process to expose the top surface of the first die, and
performing a grinding process to form a trench to expose the top surface of the second die.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a thermal interface material (TIM) in the trench and on the top surface of the first die,
wherein a thickness of the TIM over the first die is less than a thickness of the TIM over the second die, and
wherein the heat sink is bonded to the first die and the second die by the TIM.

### Claim 18

A package structure, comprising:
a substrate;
an interposer bonded to the substrate;
a first die and a second die bonded to the interposer;
a thermal interface material (TIM) layer disposed over the first die and the second die; and
a heat sink bonded to the TIM layer,
wherein a thickness of a first portion of the TIM over the first die is greater than a thickness of a second portion of the TIM over the second die.

### Claim 19 (depends on 18)

The package structure of claim 18, wherein the first die is bonded to the interposer by first micro bumps and the second die is bonded to the interposer by second micro bumps,
wherein the first micro bumps and the second micro bumps have different heights.

### Claim 20 (depends on 18)

The package structure of claim 18, wherein the first die is a system-on-chip (SoC) die or a system-on-integrated-chip (SoIC) die, and the second die is a high bandwidth memory (HBM) die.