# US 2026/0076255 A1 · Stacked semiconductor die architecture with redistribution layers on dies stacked orthogonal to a base die or substrate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2026/0076255 A1
- Document ID: US20260076255A1
- Status: Published application
- Kind: A1
- Application number: 18/828,130
- Filed: 2024-09-09
- Published: 2026-03-12
- Earliest claimed: 2024-09-09
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Joe F. Walczyk; Pooya Tadayon; Xavier Francois Brun
- Web page: https://patentgrep.com/patent/US20260076255A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/66: Conductive materials thereof
- H10W 72/019: {of bond pads}
- H05K 1/181: associated with surface mounted components
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 72/0198: {batch processes}
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/735: {between a chip and a laterally-adjacent insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Microelectronic assembly architectures including a die stack in which each die includes a redistribution layer, and the die stack is positioned such that the face of each die is perpendicular to a face of a base, are provided. Each die has a first face and a second face opposite the first face, and an edge extending between the first and second faces. A redistribution layer is deposited on the first face of each die. The faces of each die in the die stack are parallel to the faces of the other dies. The die stack is positioned on the base such that the faces of each die are orthogonal to the face of the base. Each die can have a conductive contact on a bottom edge, and the conductive contact can be coupled to the respective redistribution layer on the die and to a conductive contact on the base.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a base having a top face, wherein the base is one of a substrate and a base die;
a die stack including:
a first die having a first face, a second face, and a bottom edge extending between the first face and the second face,
a conductive contact on the bottom edge of the first die,
a redistribution layer on the first face of the first die coupled to the conductive contact, and
a second die having a first face and a second face opposite the first face, the second face of the second die parallel to the first face of the first die;
wherein the die stack is coupled to the top face of the base; and
a solder on the base, wherein the conductive contact is coupled to the solder;
wherein the first face of the first die and the second face of the second die are substantially perpendicular to the top face of the base.

### Claim 2 (depends on 1)

The microelectronic assembly of claim 1, wherein the first die is a memory die.

### Claim 3 (depends on 1)

The microelectronic assembly of claim 1, wherein the redistribution layer includes a plurality of interconnected conductive pads.

### Claim 4 (depends on 1)

The microelectronic assembly of claim 1, further comprising an adhesive between the redistribution layer and the second face of the second die.

### Claim 5 (depends on 4)

The microelectronic assembly of claim 4, wherein the adhesive is an insulator material.

### Claim 6 (depends on 1)

The microelectronic assembly of claim 1, further comprising an insulator material between the bottom edge of the first die and the conductive contact.

### Claim 7 (depends on 1)

The microelectronic assembly of claim 1, wherein the conductive contact is a first conductive contact and further comprising a base conductive contact on the top face of the base.

### Claim 8 (depends on 1)

The microelectronic assembly of claim 1, wherein the solder is coupled to the base conductive contact.

### Claim 9 (depends on 1)

The microelectronic assembly of claim 1, wherein the redistribution layer includes a copper material.

### Claim 10 (depends on 1)

The microelectronic assembly of claim 1, wherein the redistribution layer includes a patterned conductive material.

### Claim 11 (depends on 1)

The microelectronic assembly of claim 1, further comprising a spacer layer between the redistribution layer and the second face of the second die, wherein the spacer layer is between about one tenth and one times a width of the first die.

### Claim 12 (depends on 1)

The microelectronic assembly of claim 1, wherein an area of the first face of the first die is substantially the same as an area of the second face of the first die, and wherein the area of the first face of the first die is about five times to about fifty times larger than an area of the bottom edge of the first die.

### Claim 13 (depends on 1)

The microelectronic assembly of claim 1, further comprising an insulator material on the base and around a portion of the die stack.

### Claim 14

A microelectronic assembly, comprising:
a die stack including:
a first die having a first face and a second face opposite the first face, and a bottom edge extending between the first face and the second face of the first die,
a redistribution layer on the first face of the first die,
a second die having a first face and a second face opposite the first face, the second face of the second die parallel to the first face of the first die, and
a spacer layer between the first face of the first die and the second face of the second die;
a base having a top face and a conductive contact, wherein the bottom edge of the first die is substantially parallel to the top face of the base, and the first face of the first die and the second face of the second die are substantially perpendicular to the top face of the base; and
a solder coupled to the conductive contact and the redistribution layer.

### Claim 15 (depends on 14)

The microelectronic assembly of claim 14, wherein the conductive contact is a base conductive contact and wherein the die stack further includes a first conductive contact at the bottom edge of the first die coupled to the redistribution layer.

### Claim 16 (depends on 14)

The microelectronic assembly of claim 14, wherein the redistribution layer includes a plurality of conductive pads.

### Claim 17 (depends on 14)

The microelectronic assembly of claim 14, wherein the redistribution layer is in the spacer layer and wherein the spacer layer is an insulator material.

### Claim 18

A provides a process of making a semiconductor package substrate, the method comprising:
providing a die stack including:
a first die having a first face, a second face, and a bottom edge extending between the first face and the second face,
a first conductive contact adjacent to the bottom edge of the first die,
a redistribution layer on the first face of the first die, the redistribution layer coupled to the first conductive contact,
a second die having a first face and a second face opposite the first face, the second face of the second die parallel to the first face of the first die, and
positioning the die stack on a top face of a base, with the first face of the first die and the second face of the second die substantially perpendicular to the top face of the base; and
coupling the first conductive contact with a base conductive contact on the base.

### Claim 19 (depends on 18)

The process of claim 18, further comprising providing a solder material between the first conductive contact and the base conductive contact.

### Claim 20 (depends on 18)

The process according to claim 18, further comprising providing an insulator material between the bottom edge of the first die and the first conductive contact.