# US 2026/0076223 A1 · Semiconductor structure and method manufacturing the same

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- Number: US 2026/0076223 A1
- Document ID: US20260076223A1
- Status: Published application
- Kind: A1
- Application number: 19/394,883
- Filed: 2025-11-20
- Published: 2026-03-12
- Earliest claimed: 2019-06-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Fa Chen; Sung-Feng Yeh; Tzuan-Horng Liu; Chao-Wen Shih
- Web page: https://patentgrep.com/patent/US20260076223A1

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W 72/30: Die-attach connectors
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first semiconductor device and a second semiconductor device, wherein the first semiconductor device is disposed over the second semiconductor device;
a connection device, disposed over the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device comprises a first substrate and conductive vias penetrating through the first substrate and electrically coupled to the second semiconductor device; and
an insulating encapsulation, laterally encapsulating the first semiconductor device and the connection device, wherein the insulating encapsulation is in contact with the second semiconductor device, and a sidewall of the insulating encapsulation is substantially aligned with a sidewall of the second semiconductor device,
wherein the first semiconductor device is electrically coupled to the second semiconductor device through the conductive vias of the connection device.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a redistribution circuit structure, disposed over the second semiconductor device, wherein the first semiconductor device and the connection device are between the redistribution circuit structure and the second semiconductor device,
wherein the connection device and the first semiconductor device are an integral piece, and the connection device is joined to the first semiconductor device, wherein the backside of the first semiconductor device is completely covered by the frontside of the second semiconductor device,
wherein a frontside of the first semiconductor device is physically contacted to a surface of the redistribution circuit structure, and the frontside of the first semiconductor device is opposite to the backside of the first semiconductor device and comprises surfaces of first connecting vias and a surface of a first protection layer substantially coplanar to the surfaces of the first connecting vias.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein a shape of the connection device is a closed, continuous frame shape laterally surrounding the first semiconductor device.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein the insulating encapsulation is between the second semiconductor device and the redistribution circuit structure, and
wherein the first semiconductor device is separated from the insulating encapsulation by the connection device, and the conductive vias are separated from the insulating encapsulation by the first substrate.

### Claim 5 (depends on 2)

The semiconductor structure of claim 2, wherein:
the first substrate comprises a first portion and a second portion connected to the first portion,
the connection device further comprises:
a first interconnect structure, disposed over a first surface of the first portion of the first substrate and electrically coupled to the conductive vias, wherein the conductive vias penetrate through the first portion of the first substrate by extending from the first surface toward a second surface of the first portion of the first substrate, and the first surface is opposite to the second surface, wherein a first end surface of each of the conductive vias is substantially coplanar to the first surface of the first portion of the first substrate, and a second end surface of each of the conductive vias is protruded out of the second surface, and
the first semiconductor device comprises:
the second portion of the first substrate;
a second interconnect structure, disposed over the second portion of the first substrate and electrically coupled to the first interconnect structure; and
the first connecting vias, disposed over and electrically coupled to the second interconnect structure, wherein the first semiconductor device is electrically coupled to the redistribution circuit structure through the second interconnect structure and the first connecting vias,
wherein the connection device is electrically coupled to the first semiconductor device through the first interconnect structure and the second interconnect structure, and is electrically coupled to the redistribution circuit structure through the first semiconductor device.

### Claim 6 (depends on 2)

The semiconductor structure of claim 2, wherein:
the first substrate comprises a first portion and a second portion connected to the first portion,
the connection device further comprises:
a first interconnect structure, disposed over the first portion of the first substrate, wherein the conductive vias penetrate through the first portion of the first substrate and the first interconnect structure by extending from the first interconnect structure toward the first portion of the first substrate, wherein a first end surface of each of the conductive vias is substantially coplanar to a surface of the first interconnect structure away from the first portion of the first substrate, and a second end surface of each of the conductive vias is protruded out of a surface of the first portion of the first substrate away from the first interconnect structure, wherein the connection device is electrically coupled to the redistribution circuit structure through the conductive vias, and
the first semiconductor device comprises:
the second portion of the first substrate, having at least one of an active device or a passive device formed therein;
a second interconnect structure, disposed over the second portion of the first substrate and electrically coupled to the at least one of an active device or a passive device and the first interconnect structure; and
the first connecting vias, disposed over and electrically coupled to the second interconnect structure, wherein the first semiconductor device is electrically coupled to the redistribution circuit structure through the second interconnect structure and the first connecting vias,
wherein the connection device is electrically coupled to the first semiconductor device through the redistribution circuit structure.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a redistribution circuit structure, over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device,
wherein the connection device comprises a plurality of connection devices distant from the first semiconductor device.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the plurality of connection devices are arranged into a pattern laterally surrounding a perimeter of the first semiconductor device.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein the insulating encapsulation is located between the second semiconductor device and the redistribution circuit structure, and
wherein the first semiconductor device is separated from the plurality of connection devices by the insulating encapsulation, and the conductive vias are separated from the insulating encapsulation by the first substrate.

### Claim 10 (depends on 7)

The semiconductor structure of claim 7, wherein:
each of the plurality of connection devices further comprises:
a first interconnect structure, disposed over a first surface of the first substrate and electrically coupled to the conductive vias, wherein the conductive vias penetrate through the first substrate by extending from the first surface toward a second surface of the first substrate, and the first surface is opposite to the second surface, wherein a first end surface of each of the conductive vias is substantially coplanar to the first surface of the first substrate, and a second end surface of each of the conductive vias is protruded out of the second surface; and
a plurality of first connecting vias, disposed over and electrically coupled to the first interconnect structure, wherein the connection devices are electrically coupled to the redistribution circuit structure through the first interconnect structure and the plurality of first connecting vias, and
the first semiconductor device comprises:
a second substrate, having at least one of an active device or a passive device formed therein;
a second interconnect structure, disposed over the second substrate and electrically coupled to the at least one of an active device or a passive device; and
a plurality of second connecting vias, disposed over and electrically coupled to the second interconnect structure, wherein the first semiconductor device is electrically coupled to the redistribution circuit structure through the second interconnect structure and the plurality of second connecting vias,
wherein the plurality of connection devices are electrically coupled to the first semiconductor device through the redistribution circuit structure.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein:
each of the plurality of connection devices further comprises:
a first interconnect structure, disposed over the first substrate, wherein the conductive vias penetrate through the first substrate and the first interconnect structure by extending from the first interconnect structure toward the first substrate, wherein a first end surface of each of the conductive vias is substantially coplanar to a surface of the first interconnect structure away from the first substrate, and a second end surface of each of the conductive vias is protruded out of a surface of the first substrate away from the first interconnect structure, wherein the connection device is electrically coupled to the redistribution circuit structure through the conductive vias, and
the first semiconductor device comprises:
a second substrate, having at least one of an active device or a passive device formed therein;
a second interconnect structure, disposed over the second substrate and electrically coupled to the at least one of an active device or a passive device; and
a plurality of first connecting vias, disposed over and electrically coupled to the second interconnect structure, wherein the first semiconductor device is electrically coupled to the redistribution circuit structure through the second interconnect structure and the plurality of first connecting vias,
wherein the plurality of connection devices are electrically coupled to the first semiconductor device through the redistribution circuit structure.

### Claim 12

A semiconductor structure, comprising:
a first integrated circuit component comprising:
a device portion; and
at least one bridge portion, wherein the device portion is aside of the at least one bridge portion;
a second integrated circuit component, disposed underneath the first integrated circuit component, wherein the device portion is electrically coupled to the second integrated circuit component through the at least one bridge portion;
an insulating encapsulation, laterally encapsulating the device portion and the at least one bridge portion, wherein the insulating encapsulation is in contact with the second integrated circuit component, and a sidewall of the insulating encapsulation is substantially aligned with a sidewall of the second integrated circuit component;
a redistribution circuit structure, disposed over and connected to the first integrated circuit component, wherein the redistribution circuit structure is electrically coupled to the second integrated circuit component through the first integrated circuit component; and
conductive terminals, disposed over and connecting to the redistribution circuit structure, wherein the redistribution circuit structure is located between the first integrated circuit component and the conductive terminals.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the at least one bridge portion is joined to the device portion.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein the at least one bridge portion is separated from the device portion.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, further comprising:
a circuit substrate, disposed over the redistribution circuit structure and being electrically coupled to the redistribution circuit structure through the conductive terminals,
wherein the circuit substrate is electrically coupled to the first integrated circuit component through the redistribution circuit structure and is electrically coupled to the second integrated circuit component through the redistribution circuit structure and the first integrated circuit component.

### Claim 16

A semiconductor structure, comprising:
a first integrated circuit component comprising:
a device portion; and
at least one bridge portion, wherein the device portion is aside of the at least one bridge portion;
a second integrated circuit component, disposed over a side of the first integrated circuit component, wherein the device portion is electrically coupled to the second integrated circuit component through the at least one bridge portion;
a redistribution circuit structure, disposed over an opposite side of the first integrated circuit component, wherein the redistribution circuit structure is electrically coupled to the second integrated circuit component through the first integrated circuit component; and
a circuit substrate, disposed over the redistribution circuit structure and being electrically coupled to the first integrated circuit component through the redistribution circuit structure.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, further comprising:
an insulating encapsulation, laterally encapsulating the device portion and the at least one bridge portion, wherein the insulating encapsulation is in contact with the second integrated circuit component,
wherein a sidewall of the insulating encapsulation, a sidewall of the second integrated circuit component and a sidewall of the redistribution circuit structure are substantially aligned to each other.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, further comprising:
a plurality of first conductive terminals, disposed between and electrically coupling the redistribution circuit structure and the circuit substrate; and
a plurality of second conductive terminals, disposed over and electrically coupled to the circuit substrate, wherein the circuit substrate is between and electrically coupling the plurality of first conductive terminals and the plurality of second conductive terminals.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, further comprising:
an interposer, disposed between the redistribution circuit structure and the circuit substrate;
a plurality of first conductive terminals, disposed between and electrically coupling the redistribution circuit structure and the interposer;
a plurality of second conductive terminals, disposed between and electrically coupling the interposer and the circuit substrate; and
a plurality of third conductive terminals, disposed over and electrically coupled to the circuit substrate, wherein the circuit substrate is between and electrically coupling the plurality of second conductive terminals and the plurality of third conductive terminals.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, further comprising:
a sub-package, comprising:
the circuit substrate;
at least one semiconductor dies, disposed over and electrically coupled to the circuit substrate; and
an encapsulant, disposed over the circuit substrate and encapsulating the at least one semiconductor dies; and
a plurality of conductive terminals, disposed between and electrically coupling the redistribution circuit structure and the circuit substrate, the circuit substrate being between the redistribution circuit structure and an encapsulant.