# US 2026/0076220 A1 · Fan-out wafer level packaging unit

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- Number: US 2026/0076220 A1
- Document ID: US20260076220A1
- Status: Published application
- Kind: A1
- Application number: 19/315,687
- Filed: 2025-09-01
- Published: 2026-03-12
- Earliest claimed: 2024-09-10
- Assignees: Walton Advanced Engineering Inc.
- Applicants: Walton Advanced Engineering, Inc.
- Inventors: HONG-CHI YU; CHUN-JUNG LIN; RUEI-TING GU
- Web page: https://patentgrep.com/patent/US20260076220A1

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/874: {On different surfaces}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A fan-out wafer-level packaging (FOWLP) unit having a substrate, at least one chip, a dielectric layer, at least one conductive circuit, and an outer protective layer is provided. The chip includes a die, chip conductive circuits, a chip dielectric layer, chip bonding pads, a first chip surface, and a second chip surface. The die is electrically connected with the outside through the die pad. The conductive circuits are formed by a metal paste filled into at least one slot of the dielectric layer and grinding of the metal paste. The conductive circuits form a bonding pad in each of openings of the outer protective layer. The chip is electrically connected to the outside through the bonding pads located around a chip area on the second chip surface of the chip. Thereby problems of the FOWLP module available now including higher manufacturing cost and less environmental benefit can be solved.

## Claims

### Claim 1

A fan-out wafer level packaging (FOWLP) unit comprising
a substrate provided with a first surface and a second surface opposite to the first surface;
at least one chip having a die, a plurality of chip conductive circuits, a chip dielectric layer, a plurality of chip bonding pads, a first chip surface, and a second chip surface; wherein the chip is arranged at the substrate by the first chip surface; wherein the chip bonding pads are disposed on the second chip surface and a range perpendicular to the second chip surface of the chip is defined as a chip area; wherein the die is provided with at least one die pad so that the die is electrically connected with the outside through the die pad, the chip conductive circuits, and the chip bonding pads in turn;
an dielectric layer mounted to the second surface of the substrate and covering the chip; at least one slot extending horizontally formed on the dielectric layer and used for allowing the corresponding chip bonding pad to be exposed;
at least one conductive circuit formed by a metal paste filled into the slots; wherein the conductive circuit is electrically connected to the chip bonding pads; and
an outer protective layer arranged over the dielectric layer and the conductive circuit and having a plurality of openings; wherein at least one of the openings is located around the chip area on the second chip surface of the chip;
wherein the conductive circuit is exposed through the opening correspondingly to form a bonding pad in the openings; wherein the chip is electrically connected with the outside through the chip bonding pads, the conductive circuit, and the bonding pads located around the chip area on the second chip surface of the chip; thereby the FOWLP unit is formed;
wherein a method of manufacturing the FOWLP unit comprising the steps of:
Step S1: providing a substrate; wherein the substrate having a first surface and a second surface opposite to each other;
Step S2: disposing a plurality of chips on the second surface of the substrate with an interval between the two adjacent chip; wherein the chip consists of a die, a plurality of chip conductive circuits, a chip dielectric layer, a plurality of chip bonding pads, a first chip surface, and a second chip surface; wherein the chip is arranged at the substrate by the first chip surface; wherein the chip bonding pads are disposed on the second chip surface and a range perpendicular to the second chip surface of the chip is defined as a chip area; wherein the die is provided with at least one die pad; the die is electrically connected with the outside through the die pad, the chip conductive circuit, and the chip bonding pads in turn; wherein a method of manufacturing the chip further includes the steps of providing a wafer having a plurality of dies each of which is provided with at least one die pad; then disposing a first dielectric layer over the dies and forming at least one slot on the first dielectric layer; next filling a metal paste into the slot of the first dielectric layer and allowing a level of the metal paste higher than a surface of the first dielectric layer; later grinding the metal paste with the level higher than the surface of the surface of the first dielectric layer to make a surface of the metal paste flush with the surface of the first dielectric layer and form a plurality of first conductive circuits; wherein the first conductive circuits are electrically connected to the die pads of the dies; then arranging a second dielectric layer over the first dielectric layer and forming at least one slot on the second dielectric layer; next filling a metal paste into the slot of the second dielectric layer and allowing a level of the metal paste higher than a surface of the second dielectric layer; later grinding the metal paste with the level higher than the surface of the surface of the second dielectric layer to make a surface of the metal paste flush with the surface of the second dielectric layer and form a plurality of second conductive circuits; wherein the second conductive circuits are electrically connected to the first conductive circuits; and lastly performing cutting and diving the wafer into a plurality of chips; wherein a plurality of chip conductive circuits is formed by the first conductive circuits and the second conductive circuits; wherein a chip dielectric layer is formed by the first dielectric layer and the second dielectric layer;
Step S3: disposing a dielectric layer on the second surface of the substrate and allowing the dielectric layer covering the chip; wherein the dielectric layer is provided with at least one slot extending in a horizontal direction and used for allowing the chip bonding pad to be exposed;
Step S4: filling a metal paste into the slot of the dielectric layer and allowing a level of the metal paste higher than a surface of the dielectric layer;
Step S5: grinding the metal paste with the level higher than the surface of the dielectric layer to make a surface of the metal paste flush with the surface of the dielectric layer and form a plurality of conductive circuits;
Step S6: paving an outer protective layer over the dielectric layer;
Step S7: forming a plurality of openings on the outer protective layer and allowing at least one of the openings to be located around the chip area on the second chip surface of the chip so that the conductive circuits are exposed through the openings to form a bonding pad in each of the openings; and
Step S8: performing cutting to form a plurality of FOWLP units.

### Claim 2 (depends on 1)

The FOWLP unit as claimed in claim 1, wherein a bump is mounted in each of the openings and disposed on the bonding pad.

### Claim 3 (depends on 2)

The FOWLP unit as claimed in claim 2, wherein a solder ball is disposed on each of the bumps.

### Claim 4 (depends on 3)

The FOWLP unit as claimed in claim 3, wherein the FOWLP unit is electrically connected and mounted to a printed circuit board (PCB) by the solder balls.

### Claim 5 (depends on 1)

The FOWLP unit as claimed in claim 1, wherein the metal pastes which form the first conductive circuits and the second conductive circuits include silver paste, nano-scale silver paste, copper paste, and nano-scale copper paste.

### Claim 6 (depends on 1)

The FOWLP unit as claimed in claim 1, wherein the substrate includes a silicon substrate, a glass substrate, and a ceramic substrate.

### Claim 7 (depends on 1)

The FOWLP unit as claimed in claim 1, wherein the metal paste which forms the conductive circuits includes silver paste, nano-scale silver paste, copper paste, and nano-scale copper paste.

### Claim 8 (depends on 1)

The FOWLP unit as claimed in claim 1, wherein the first chip surface of the chip is disposed on the second surface of the substrate by a die attach film (DAF).