# US 2026/0076217 A1 · Semiconductor package substrate including graphene layer, method of manufacturing the semiconductor package substrate, and semiconductor package including the semiconductor package substrate

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- Number: US 2026/0076217 A1
- Document ID: US20260076217A1
- Status: Published application
- Kind: A1
- Application number: 19/240,074
- Filed: 2025-06-17
- Published: 2026-03-12
- Earliest claimed: 2024-06-18
- Assignees: Haesung Ds Co., Ltd.
- Applicants: Haesung Ds Co., Ltd.
- Inventors: Min PARK; Su Yeon SON; Ho Sang YU; Jin Woo LEE; Hyun Ji YUN
- Web page: https://patentgrep.com/patent/US20260076217A1

## CPC

- H10W 70/457: {of metallic layers on leadframes}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 70/04: of leadframes
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package substrate includes a base substrate including a conductive material, a die pad portion, and a lead portion, a metal catalyst layer disposed on the base substrate, and a graphene layer disposed on the metal catalyst layer, wherein the semiconductor package substrate has a Vickers hardness of 135 to 150.

## Claims

### Claim 1

A semiconductor package substrate comprising:
a base substrate comprising a conductive material, a die pad portion, and a lead portion;
a metal catalyst layer disposed on the base substrate; and
a graphene layer disposed on the metal catalyst layer,
wherein the semiconductor package substrate has a Vickers hardness of 135 to 150.

### Claim 2 (depends on 1)

The semiconductor package substrate of claim 1, wherein the metal catalyst layer includes at least one of copper (Cu), nickel (Ni), silver (Ag), gold (Au), titanium (Ti), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), iridium (Ir), and platinum (Pt).

### Claim 3 (depends on 1)

The semiconductor package substrate of claim 1, wherein the base substrate includes copper (Cu).

### Claim 4 (depends on 1)

The semiconductor package substrate of claim 1, wherein the graphene layer is directly disposed on the metal catalyst layer.

### Claim 5 (depends on 4)

The semiconductor package substrate of claim 4, wherein no oxide layer is disposed between the graphene layer and the metal catalyst layer.

### Claim 6 (depends on 1)

The semiconductor package substrate of claim 1, wherein the metal catalyst layer is disposed on at least one of a first surface of the base substrate, a second surface located on the opposite side of the first surface, and a third surface connecting the first surface to the second surface.

### Claim 7 (depends on 6)

The semiconductor package substrate of claim 6, wherein the graphene layer is disposed on at least one of a first surface of the metal catalyst layer, a second surface located on the opposite side of the first surface, and a third surface connecting the first surface to the second surface.

### Claim 8 (depends on 1)

The semiconductor package substrate of claim 1, wherein a surface energy of the graphene layer is 0.4 mJ/m2 to 115 mJ/m2.

### Claim 9 (depends on 1)

The semiconductor package substrate of claim 1, wherein at least a part of an upper surface and a lower surface of the base substrate has fine curves.

### Claim 10 (depends on 1)

A semiconductor package comprising:
the semiconductor package substrate according to claim 1;
a semiconductor chip disposed on the die pad portion; and
a bonding wire connecting the semiconductor chip to the lead portion, wherein the bonding wire is in direct contact with the graphene layer.