# US 2026/0076207 A1 · Selective backside etch for 3-d ic stack > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076207 A1 - Document ID: US20260076207A1 - Status: Published application - Kind: A1 - Application number: 18/830,463 - Filed: 2024-09-10 - Published: 2026-03-12 - Earliest claimed: 2024-09-10 - Assignees: pSemi Corporation - Applicants: pSemi Corporation - Inventors: Saloni CHAURASIA; Shishir RAY; Panglijen CANDRA - Web page: https://patentgrep.com/patent/US20260076207A1 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10D 88/01: {Manufacture or treatment} - H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates} - H10P 50/242: {of Group IV materials} - H10P 72/74: {using temporarily an auxiliary support} - H10P 90/1914: {using bonding} - H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers} - H10W 20/42: Vias, e.g. via plugs - H10W 90/00: Package configurations - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Integrated circuit structures and fabrication methods that substantially prevent or mitigate damage that plasma etching may cause to the FETs of a top integrated circuit in a 3-D integrated circuit (IC) stack. Embodiments of such IC structures include (1) use of substrate contacts (S-contacts) within the top integrated circuit, ICT, of the 3-D IC stack connected to the gates of FETs that may be damaged by plasma etching, and (2) selective retention of the substrate/handle wafer of ICT aligned and in electrical contact with such S-contacts so as to conduct plasma charge away from the gate oxide of the protected FETs. In addition, the novel integrated circuit structures provide an additional benefit by providing thermal dissipation paths (heat sinks) for the 3-D IC stack. ## Claims ### Claim 1 A three-dimensional integrated circuit (IC) stack, including: (a) a first IC including a bonding face; and (b) a second IC including: (1) a bonding face; (2) at least one substrate contact electrically coupled to a corresponding gate of a field-effect transistor (FET) within the second IC; and (3) at least one patterned post-etching handle remnant aligned and in electrical contact with a corresponding one of the at least one substrate contact; wherein the bonding face of the second IC is bonded to the bonding face of the first IC. ### Claim 2 (depends on 1) The three-dimensional IC stack of claim 1, wherein the first IC and/or the second IC are fabricated using a silicon-on-insulator fabrication process. ### Claim 3 (depends on 1) The three-dimensional IC stack of claim 1, wherein the second IC further includes a superstructure including one or more metal layers, an active layer in and on which the FET is formed, and a BOX layer. ### Claim 4 (depends on 3) The three-dimensional IC stack of claim 3, wherein the at least one substrate contact is electrically coupled between the corresponding gate of the FET and the corresponding at least one patterned post-etching handle remnant through at least one of the one or more metal layers. ### Claim 5 (depends on 3) The three-dimensional IC stack of claim 3, wherein the at least one substrate contact penetrates through the active layer and the BOX layer and is electrically coupled between at least one of the one or more metal layers and the corresponding at least one patterned post-etching handle remnant. ### Claim 6 (depends on 1) The three-dimensional IC stack of claim 1, wherein the second IC includes a die seal ring. ### Claim 7 A three-dimensional integrated circuit (IC) stack, including: (a) a first IC including a bonding face; and (b) a second IC including: (1) a superstructure including one or more metal layers, an active layer in and on which a field-effect transistor (FET) is formed, a BOX layer; and a bonding face; (2) a substrate contact electrically coupled to a gate of the FET; and (3) at least one post-etching handle remnant aligned and in electrical contact with the substrate contact; wherein the bonding face of the second IC is bonded to the bonding face of the first IC. ### Claim 8 (depends on 7) The three-dimensional IC stack of claim 7, wherein the substrate contact is electrically coupled between the gate of the FET and the post-etching handle remnant through at least one of the one or more metal layers. ### Claim 9 (depends on 7) The three-dimensional IC stack of claim 7, wherein the substrate contact penetrates through the active layer and the BOX layer and is electrically coupled between at least one of the one or more metal layers and the post-etching handle remnant. ### Claim 10 (depends on 7) The three-dimensional IC stack of claim 7, wherein the second IC includes a die seal ring. ### Claim 11 A method of fabricating a three-dimensional integrated circuit (IC) stack, including: (a) fabricating a first IC including a bonding face; and (b) fabricating a second IC including: (1) a bonding face; (2) at least one substrate contact electrically coupled to a corresponding gate of a field-effect transistor (FET) within the second IC; and (3) at least one patterned post-etching handle remnant aligned and in electrical contact with a corresponding one of the at least one substrate contact; (c) bonding the bonding face of the second IC to the bonding face of the first IC. ### Claim 12 (depends on 11) The method of claim 11, further including fabricating the first IC and/or the second IC using a silicon-on-insulator fabrication process. ### Claim 13 (depends on 11) The method of claim 11, wherein the second IC further includes a superstructure including one or more metal layers, an active layer in and on which the FET is formed, and a BOX layer. ### Claim 14 (depends on 13) The three-dimensional IC stack of claim 13, wherein the at least one substrate contact is electrically coupled between the corresponding gate of the FET and the corresponding at least one patterned post-etching handle remnant through at least one of the one or more metal layers. ### Claim 15 (depends on 13) The method of claim 13, wherein the at least one substrate contact penetrates through the active layer and the BOX layer and is electrically coupled between at least one of the one or more metal layers and the corresponding at least one patterned post-etching handle remnant. ### Claim 16 (depends on 11) The method of claim 11, wherein the second IC includes a die seal ring. ### Claim 17 A method of fabricating a three-dimensional integrated circuit (IC) stack, including: (a) fabricating a first IC including a bonding face; (b) fabricating a second IC including: (1) a bonding face; (2) a substrate/handle wafer; and (3) at least one substrate contact electrically coupled between a corresponding gate of a field-effect transistor (FET) within the second IC and the substrate/handle wafer; (c) bonding the bonding face of the second IC to the bonding face of the first IC; (d) masking and etching the substrate/handle wafer of the second IC to remove the substrate/handle wafer except for at least one post-etching handle remnant aligned and in electrical contact with a corresponding one of the at least one substrate contact; and (e) fabricating a backside structure for the second IC in regions not covered by the at least one post-etching handle remnant. ### Claim 18 (depends on 17) The method of claim 17, further including thinning the substrate/handle wafer of the second IC before masking and etching the substrate/handle wafer of the second IC. ### Claim 19 (depends on 17) The method of claim 17, further including thinning the substrate/handle wafer of the second IC after bonding the bonding face of the second IC to the bonding face of the first IC, and before masking and etching the substrate/handle wafer of the second IC. ### Claim 20 (depends on 17) The method of claim 17, further including fabricating a die seal ring as part of the second IC.