# US 2026/0076203 A1 · Semiconductor package substrate

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- Number: US 2026/0076203 A1
- Document ID: US20260076203A1
- Status: Published application
- Kind: A1
- Application number: 19/224,990
- Filed: 2025-06-02
- Published: 2026-03-12
- Earliest claimed: 2024-07-22
- Assignees: Haesung Ds Co., Ltd.
- Applicants: Haesung Ds Co., Ltd.
- Inventors: Dong Jin YOON; Sung Il KANG
- Web page: https://patentgrep.com/patent/US20260076203A1

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package substrate includes a base substrate including a conductive material and having a first groove or first trench located in a bottom surface of the base substrate, a resin filled into the first groove or first trench, a first plating layer disposed on a top surface of the base substrate, and a second plating layer disposed on the bottom surface of the base substrate, wherein the base substrate includes a stress reducing portion configured to reduce stress.

## Claims

### Claim 1

A semiconductor package substrate comprising:
a base substrate comprising a conductive material and having a first groove or first trench located in a bottom surface thereof;
a resin filled into the first groove or first trench;
a first plating layer disposed on a top surface of the base substrate; and
a second plating layer disposed on the bottom surface of the base substrate,
wherein the base substrate comprises a stress reducing portion configured to reduce stress.

### Claim 2 (depends on 1)

The semiconductor package substrate of claim 1, wherein the stress reducing portion is a slot.

### Claim 3 (depends on 1)

The semiconductor package substrate of claim 1, wherein the stress reducing portion comprises:
a first stress reducing portion formed long in a first direction; and
a second stress reducing portion formed long in a second direction different from the first direction.

### Claim 4 (depends on 3)

The semiconductor package substrate of claim 3, wherein a plurality of second stress reducing portions are provided,
wherein the plurality of second stress reducing portions are arranged within a length of the first stress reducing portion to be spaced apart from each other.

### Claim 5 (depends on 1)

The semiconductor package substrate of claim 1, wherein a plurality of stress reducing portions are provided to be spaced apart from each other,
wherein a thickness of the base substrate between adjacent stress reducing portions among the plurality of stress reducing portions is less than thicknesses of other portions of the base substrate.

### Claim 6 (depends on 5)

The semiconductor package substrate of claim 5, wherein the resin is inserted into a portion of the base substrate disposed between the stress reducing portions.

### Claim 7

A semiconductor package substrate comprising:
a base substrate comprising a conductive material and having a first groove or first trench located in a bottom surface of the base substrate;
a resin filled into the first groove or first trench; and
a plating layer disposed on the base substrate,
wherein the base substrate comprises a stress reducing portion configured to reduce stress.