# US 2026/0076189 A1 · Single Crystal Diamond Dies Packaged with Ultrathin Pocketed Semiconductor Wafer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076189 A1 - Document ID: US20260076189A1 - Status: Published application - Kind: A1 - Application number: 19/297,080 - Filed: 2025-08-12 - Published: 2026-03-12 - Earliest claimed: 2024-09-06 - Assignees: Diamond Foundry Inc. - Applicants: Diamond Foundry Inc. - Inventors: Martin Roscheisen; Jeroen Van Duren; Liubo Hong; Michael Shirk; Braden Henderson; Peter Baumgart; Tuan Mai - Web page: https://patentgrep.com/patent/US20260076189A1 ## CPC - H10W 40/254: {Diamond} - H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)} - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 40/43: by flowing gases, e.g. forced air cooling - H10W 40/776: {Arrangements for jet impingement, e.g. for spraying} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A low thermal resistance device package and heatsink assembly may include a device package containing one or more logic elements with the logic elements thermally connected to one or more diamond dies in a manner that provides a thermally conductive connection between the logic elements through the one or more diamond dies and one or more heatsinks. Each heatsink contains one or more chambers configured for a fluid heat transfer medium. A reconstituted wafer product may include a plurality of diamond dies attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond. The first wafer may be a 300 millimeters sized wafer and the diamond dies may include four sector dies arranged in four sectors of the 300 millimeters sized wafer. ## Claims ### Claim 1 A low thermal resistance device package and heatsink assembly, comprising: a device package containing one or more logic elements with the one or more logic elements thermally connected to one or more dies containing diamond in a manner that provides a thermally conductive connection between the one or more logic elements through the one or more dies containing diamond; and one or more heatsinks wherein each heatsink contains one or more chambers configured for a fluid heat transfer medium. ### Claim 2 (depends on 1) The assembly of claim 1, wherein the dies containing diamond are integrated into a reconstituted wafer product, the reconstituted wafer product comprising the one or more dies containing diamond attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond. ### Claim 3 (depends on 1) The assembly of claim 1, wherein the dies containing diamond are integrated into a temporary carrier populated with the one or more dies containing diamond. ### Claim 4 (depends on 1) The assembly of claim 1, wherein the device package includes interconnects between a first logic element and a second logic element horizontally with one or more of the interconnect technologies selected from a list consisting of: interposer, interconnect bridge, redistribution layers, and substrate. ### Claim 5 (depends on 1) The assembly of claim 1, wherein the one or more heatsinks are configured for jet impingement cooling. ### Claim 6 (depends on 5) The assembly of claim 5, wherein the one or more heatsinks configured for jet impingement cooling include a jet cooling system having a separate cooling compartment for each logic element. ### Claim 7 (depends on 6) The assembly of claim 6, wherein each cooling compartment includes one or more jet openings, one or more coolant outlets and sidewalls that isolate the compartment from neighboring compartments. ### Claim 8 (depends on 5) The assembly of claim 5, wherein the one or more heatsinks configured for jet cooling include one cooling compartment for two or more logic elements with all sprayed surfaces in one plane. ### Claim 9 (depends on 5) The assembly of claim 5, wherein the one or more heatsinks configured for jet cooling include one cooling compartment for two or more logic elements with at least one sprayed surface in a different plane than the other(s). ### Claim 10 (depends on 5) The assembly of claim 5, wherein the one or more heatsinks configured for jet cooling include two or more jet impingement coolers, each configured to cool one or more dies containing diamond. ### Claim 11 (depends on 1) The assembly of claim 1, wherein the one or more heatsinks are configured for microchannel cooling. ### Claim 12 (depends on 1) The assembly of claim 1, wherein the one or more heatsinks are configured for immersion cooling. ### Claim 13 (depends on 12) The assembly of claim 12 wherein the one or more dies containing diamond have a surface area enhancing coating or component. ### Claim 14 (depends on 1) The assembly of claim 1 wherein the one or more heatsinks are coupled to one or more stiffeners configured to stabilize the one or more heatsinks over the one or more dies containing diamond. ### Claim 15 (depends on 14) The assembly of claim 14 wherein the one or more stiffeners are connected to a circuit board underneath the one or more dies containing diamond. ### Claim 16 (depends on 14) The assembly of claim 14 wherein the one or more stiffeners are connected to a backing bracket behind a circuit board underneath the one or more dies containing diamond. ### Claim 17 (depends on 1) The assembly of claim 1 wherein the one or more heatsinks are integrated into the material of a package lid wherein the lid is optionally connected to one or more stiffeners configured to stabilize the one or more heatsinks over the one or more dies containing diamond. ### Claim 18 (depends on 1) The assembly of claim 1 wherein the one or more heatsinks are coupled to the top of a lid and wherein the lid is optionally connected to the one or more stiffeners configured to stabilize the one or more heatsinks over the one or more dies containing diamond. ### Claim 19 (depends on 2) The assembly of claim 2 wherein the one or more heatsinks are connected to the one or more dies containing diamond integrated into the reconstituted wafer and the fluid heat transfer medium is in direct contact with the one or more dies containing diamond. ### Claim 20 (depends on 19) The assembly of claim 19 wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium, contains at least one of diamond, silicon, copper, zinc, and an anti-fouling coating. ### Claim 21 (depends on 19) The assembly of claim 19 wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium is patterned to enhance its surface area and/or direct the fluid flow. ### Claim 22 (depends on 3) The assembly of claim 3 wherein the one or more heatsinks are connected to the one or more dies containing diamond originated from the temporary carrier and the fluid heat transfer medium is in direct contact with the one or more dies containing diamond. ### Claim 23 (depends on 22) The assembly of claim 22 wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium, contains at least one of diamond, silicon, copper, zinc, and an anti-fouling coating. ### Claim 24 (depends on 22) The assembly of claim 22 wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium, is patterned to enhance its surface area and/or direct the fluid flow. ### Claim 25 (depends on 1) The assembly of claim 1 wherein an outer perimeter of the one or more heatsinks is aligned with an outer perimeter of the device package. ### Claim 26 (depends on 1) The assembly of claim 1 wherein an outer perimeter of the one or more heatsinks is aligned with an outer perimeter of the logic elements located closest to the outer perimeter of the device package. ### Claim 27 (depends on 1) The assembly of claim 1 wherein the one or more heatsinks are located over the one or more logic elements and surfaces of the one or more logic elements in contact with the fluid heat transfer medium are in the same plane. ### Claim 28 (depends on 1) The assembly of claim 1 wherein the one or more heatsinks are located over the one or more logic elements and at least one surface of the surfaces of the one or more logic elements in contact with the fluid heat transfer medium is in a different plane than the other logic element(s). ### Claim 29 (depends on 1) The assembly of claim 1 wherein a surface of the one or more dies containing diamond bonded to the one or more logic elements is below the top surface of one or more memory dies. ### Claim 30 (depends on 5) The assembly of claim 5 wherein the one or more heatsinks include one or more manifolds, one or more chambers, one or more inlets, and one or more outlets configured for jet impingement cooling with the fluid heat transfer medium in direct contact with the one or more dies containing diamond. ### Claim 31 (depends on 5) The assembly of claim 5 wherein the one or more heatsinks include a portion of the dies containing diamond. ### Claim 32 (depends on 11) The assembly of claim 11 wherein the one or more heatsinks include horizontal microchannels and vertical vias configured for use with a fluid heat transfer medium wherein the fluid heat transfer medium is in direct contact with a surface of the one or more dies containing diamond. ### Claim 33 (depends on 11) The assembly of claim 11 wherein the one or more heatsinks include a portion of the dies containing diamond. ### Claim 34 (depends on 1) The assembly of claim 1 wherein the one or more heatsinks include one or more nozzles configured to spray a jet of fluid heat transfer medium against a thermally conductive surface in thermal contact with one or more logic elements. ### Claim 35 (depends on 34) The assembly of claim 34 wherein at least one of the one or more nozzles is aligned with a hot spot on at least one logic element. ### Claim 36 (depends on 34) The assembly of claim 34 wherein the thermally conductive surface includes one or more patterned structures configured to improve conduction of heat to the fluid heat transfer medium. ### Claim 37 (depends on 36) The assembly of claim 36 wherein the one or more patterned structures include fins or pins coupled to the thermally conductive surface. ### Claim 38 (depends on 4) The assembly of claim 4 further comprising one or more logic units, and one or more memory units. ### Claim 39 (depends on 12) The assembly of claim 12 further comprising a condenser coupled to an outlet in the one or more heatsinks outer casing and wherein the fluid heat transfer medium is a two phase coolant. ### Claim 40 (depends on 12) The assembly of claim 12 wherein the one or more heatsinks further include one or more impellers configured to move the fluid heat transfer medium. ### Claim 41 (depends on 12) The assembly of claim 12 wherein one or more heatsinks include a fluid heat transfer medium suitable for immersion cooling, and one or more heatsinks include a fluid heat transfer medium suitable for either immersion cooling or alternative fluid heat transfer medium cooling methods. ### Claim 42 (depends on 41) The assembly of claim 41 wherein at least two heatsinks use different fluid heat transfer media from one another. ### Claim 43 (depends on 41) The assembly of claim 41 wherein at least one heatsink includes one or more nozzles configured to spray the fluid heat transfer medium against a thermally conductive surface thermally connected to one or more logic elements. ### Claim 44 (depends on 41) The assembly of claim 41 wherein at least one heatsink includes one or more microchannels and vias configured for microchannel cooling with a fluid heat transfer medium in thermal contact with a thermally conductive surface thermally connected to one or more logic elements. ### Claim 45 (depends on 41) The assembly of claim 41 wherein at least one fluid heat transfer medium is a hydrocarbon or fluorochemical. ### Claim 46 (depends on 1) The assembly of claim 1 wherein at least one fluid heat transfer medium contains water. ### Claim 47 (depends on 5) The assembly of claim 5 wherein at least one fluid heat transfer medium contains water. ### Claim 48 (depends on 2) The assembly of claim 2 wherein at least one of the first wafer and second wafer includes one or more pockets containing one or more dies containing diamond and wherein the plurality of dies containing diamond are sandwiched between the first wafer and the second wafer. ### Claim 49 (depends on 48) The assembly of claim 48 where the pockets are created in a top layer of the first wafer, or the second wafer or both the first wafer and the second wafer. ### Claim 50 (depends on 49) The assembly of claim 49 wherein the top layer contains at least one of the following materials: silicon, germanium, aluminum, tin, copper, silver, gold, zinc, silicon oxide, a sol-gel, polymer, thermoplastic, curable adhesive, molding compound, epoxies, photoresists, benzocyclobutene (BCB) derivatives, spin-on photo-dielectrics, spin-on glass, polymer-derived ceramics, silicones, and polyimides. ### Claim 51 (depends on 48) The assembly of claim 48 where at least one of the first wafer and the second wafer is a silicon wafer and the pockets are created in the silicon wafer. ### Claim 52 (depends on 48) The assembly of claim 48 where the pockets are created by additive manufacturing. ### Claim 53 (depends on 48) The assembly of claim 48 wherein the pockets each envelope at least 90 percent of each of the plurality of dies containing diamond. ### Claim 54 (depends on 48) The assembly of claim 48 wherein each pocket completely envelopes a die containing diamond and wherein the first wafer is bonded to the second wafer. ### Claim 55 (depends on 48) The assembly of claim 48 wherein the pockets extend 100 micrometers or deeper into at least one of the first wafer and second wafer. ### Claim 56 (depends on 48) The assembly of claim 48 wherein the pockets extend less than 100 micrometers but greater than 10 micrometers into at least one of the first wafer and second wafer. ### Claim 57 (depends on 2) The assembly of claim 2, wherein the thermal resistance of the reconstituted wafer product is less than 2 mm2-K/W when integrated into a final device package. ### Claim 58 (depends on 2) The assembly of claim 2, wherein the thermal resistance of the reconstituted wafer product is less than 1 mm2-K/W when integrated into a final device package. ### Claim 59 (depends on 2) The assembly of claim 2, wherein the thermal resistance of the reconstituted wafer product is less than 0.5 mm2-K/W when integrated into a final device package. ### Claim 60 (depends on 2) The assembly of claim 2 wherein the dies containing diamond include one or more single crystal diamond (SCD) dies. ### Claim 61 (depends on 60) The assembly of claim 60, wherein the dies containing diamond are all SCD dies. ### Claim 62 (depends on 60) The assembly of claim 60, wherein the one or more SCD dies are characterized by a lateral dimension of 1 centimeter or greater. ### Claim 63 (depends on 2) The assembly of claim 2, wherein the dies containing diamond include at least one polycrystalline diamond die. ### Claim 64 (depends on 2) The assembly of claim 2, wherein the dies containing diamond include at least one composite diamond die comprised of diamond and a metal, wherein the metal includes one or more of the following: copper, silver, gold, aluminum, and zinc. ### Claim 65 (depends on 2) The assembly of claim 2, wherein at least one of the dies containing diamond has a roughness on at least one side of at least 2 nanometers. ### Claim 66 (depends on 2) The assembly of claim 2 wherein the dies containing diamond vary in thickness less than 5 micrometers. ### Claim 67 (depends on 2) The assembly of claim 2, wherein first and second wafers are characterized by lateral dimensions corresponding to those of a standard-sized semiconductor wafer. ### Claim 68 (depends on 2) The assembly of claim 2, wherein the first and second wafers are silicon wafers. ### Claim 69 (depends on 2) The assembly of claim 2, wherein at least one of the first and second wafers is characterized by a thickness of less than 100 micrometers. ### Claim 70 (depends on 2) The assembly of claim 2, wherein at least one of the first and second wafers is characterized by a thickness of less than 10 micrometers. ### Claim 71 (depends on 2) The assembly of claim 2, wherein a layer of copper, aluminum, or silicon carbide is sandwiched between the dies containing diamond and a first wafer, wherein the copper, aluminum, or silicon carbide, is at least 100 micrometers thick. ### Claim 72 (depends on 2) The assembly of claim 2 wherein the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers by either: thermocompression bonding (TCB), soldering, eutectic bonding, transient liquid phase bonding (TLPB), sintering, surface activated bonding (SAB), atomic diffusion bonding (ADB), plasma assisted bonding (PAB), ultrasonic bonding (UB), brazing, or adhesive bonding. ### Claim 73 (depends on 2) The assembly of claim 2 wherein either the first wafer, the second wafer, or both the first wafer and the second wafer are silicon wafers bonded to the dies containing diamond by surface melting the first wafer, the second wafer or both the first wafer and the second wafer. ### Claim 74 (depends on 2) The assembly of claim 2 wherein either the first wafer, the second wafer, or both wafers are bonded to the dies containing diamond with a multi-layer material made out of nickel and aluminum, aluminum and titanium, titanium and silicon, boron and titanium, or aluminum and palladium. ### Claim 75 (depends on 2) The assembly of claim 2 further comprising a smoothening material coupled to each of the plurality of dies containing diamond, wherein the smoothening material is a semiconductor smoothening layer and the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers by either: surface activated bonding (SAB), atomic diffusion bonding (ADB), plasma assisted bonding (PAB), laser assisted bonding (LAB), Flash Lamp assisted bonding (FLAB), or adhesive bonding. ### Claim 76 (depends on 2) The assembly of claim 2 wherein the smoothening material is a dielectric and the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers by either: surface activated bonding (SAB), atomic diffusion bonding (ADB), plasma assisted bonding (PAB), or adhesive bonding. ### Claim 77 (depends on 2) The assembly of claim 2, wherein the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers using a bond material. ### Claim 78 (depends on 77) The assembly of claim 77, wherein the bond material includes copper, silicon, germanium, silver, zinc, or a dielectric. ### Claim 79 (depends on 2) The assembly of claim 2 wherein at least one of the plurality of dies containing diamond are located in an area of the reconstituted wafer product corresponding to a hot spot in one or more logic elements when the reconstituted wafer product is bonded with the one or more logic elements. ### Claim 80 (depends on 2) The assembly of claim 2, wherein at least one of the plurality of dies containing diamond is located in an area of the reconstituted wafer product corresponding to the location of one or more logic elements that are known good dies when the reconstituted wafer product is bonded with the one or more logic elements. ### Claim 81 (depends on 2) The assembly of claim 2 further comprising one or more dummy dies sandwiched between the first and second wafer wherein the dummy dies are placed on locations corresponding to one or more logic elements that are not known good dies when the reconstituted wafer product is bonded with the one or more logic elements. ### Claim 82 (depends on 2) The assembly of claim 2 further comprising one or more dummy dies sandwiched between the first wafer and the second wafer wherein the dummy dies are placed near an edge of the first wafer and the second wafer. ### Claim 83 (depends on 2) The assembly of claim 2 wherein either the first wafer, the second wafer, or both the first wafer and the second wafer are silicon wafers bonded to the dies containing diamond by either laser assisted heating, flash lamp heating, or both. ### Claim 84 (depends on 83) The assembly of claim 83 wherein the reconstituted wafer further comprises a heat source absorption layer located at the bond interface wherein the heat source absorption layer contains at least one of the following elements: silicon, germanium, aluminum, tin, copper, silver, or gold. ### Claim 85 (depends on 2) The assembly of claim 2 wherein either the first wafer, the second wafer, or both the first wafer and the second wafer are silicon wafers bonded to the dies containing diamond by QCW or CW laser heating. ### Claim 86 (depends on 2) The assembly of claim 2, wherein one or both wafers are silicon wafers, and where the crystal orientation of one or both silicon wafers is either (100), (111), or (110), and the silicon originates from either the Czochralski (CZ) method or the Float Zone (FZ) method. ### Claim 87 (depends on 2) The assembly of claim 2, wherein the gaps are filled partially or completely by one or more of the following methods: plating, plasma spraying, through-hole wafer, pocketed wafer, curable adhesive or polymer, thermoplastic polymer, underfill materials, sealants, spin-on dielectrics. ### Claim 88 (depends on 2) The assembly of claim 2, wherein the two or more dies containing diamond are placed on the first wafer near each other based on matching die thickness resulting in a gradual change in die thickness from wafer side to side, or wafer center to edge. ### Claim 89 (depends on 2) The assembly of claim 2, wherein the one or more dies containing diamond are placed on a first wafer, and the surfaces of the dies containing diamond facing away from the first wafer are deposited with a precursor for bonding to a logic wafer with the precursor containing one of the following: titanium, chromium, nickel, tantalum, or silicon. ### Claim 90 A reconstituted wafer product, comprising: a plurality of dies containing diamond attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond, wherein the first wafer is a 300 millimeters sized wafer and the plurality of dies containing diamond include four sector dies arranged in four sectors of the 300 millimeters sized wafer. ### Claim 91 (depends on 90) The product of claim 90 wherein each of the four sector dies comprises less than an entire quadrant. ### Claim 92 (depends on 90) The product of claim 90 wherein each of the four sectors includes a cut corner. ### Claim 93 (depends on 90) The product of claim 90 further comprising one or more logic elements formed in the first wafer or the second wafer. ### Claim 94 (depends on 90) The product of claim 90, further comprising one or more vias through the wafer. ### Claim 95 (depends on 90) The product of claim 90 compatible with silicon transistor fabrication process conditions. ### Claim 96 (depends on 1) The assembly of claim 1 wherein the dies containing diamond each have a thickness of between 100 micrometers and 800 micrometers. ### Claim 97 (depends on 1) The assembly of claim 1 wherein at least one of the dies containing diamond has a thermal conductivity higher than 2000 W/m-K. ### Claim 98 (depends on 1) The assembly of claim 1 wherein a main surface of at least one of the one or more dies containing diamond includes a crystal orientation of (100), (110), (111), or (113).