# US 2026/0076186 A1 · Power semiconductor devices

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- Number: US 2026/0076186 A1
- Document ID: US20260076186A1
- Status: Published application
- Kind: A1
- Application number: 19/055,217
- Filed: 2025-02-17
- Published: 2026-03-12
- Earliest claimed: 2024-09-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mingu KO; Taehun KIM; Younghwan PARK; Jeonghwan PARK; Sewoong OH
- Web page: https://patentgrep.com/patent/US20260076186A1

## CPC

- H10W 40/253: {Semiconductors}
- H10D 8/60: Schottky-barrier diodes
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/8325: {Silicon carbide}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H10D 8/051: {of Schottky diodes}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10W 72/07554: {changes in dispositions}
- H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 90/00: Package configurations
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A power semiconductor device includes a substrate including SiC of a first conductivity type and including a first region and a second region, a drift layer of the first conductivity type on the substrate and in the first and second regions, a well region of a second conductivity type on the drift layer and in in the first region, a source region of the first conductivity type within the well region, a gate electrode on and extending along an upper surface of the well region, a source electrode connected to the source region in the first region, a metal layer connected to the drift layer in the second region, and a passivation layer covering the source electrode and the metal layer. The passivation layer defines a recessed portion between the first region and the second region.

## Claims

### Claim 1

A power semiconductor device comprising:
a substrate including SiC of a first conductivity type, the substrate including a first region and a second region;
a drift layer of the first conductivity type on the substrate, the drift layer being in the first region and the second region;
a well region of a second conductivity type on the drift layer, the well region being in the first region;
a source region of the first conductivity type within the well region;
a gate electrode on and extending along an upper surface of the well region;
a source electrode connected to the source region in the first region;
a metal layer connected to the drift layer in the second region; and
a passivation layer covering the source electrode and the metal layer,
wherein the passivation layer defines a recessed portion between the first region and the second region.

### Claim 2 (depends on 1)

The power semiconductor device of claim 1, wherein the first region includes a first type circuit element, and the second region includes a second type circuit element different from the first type circuit element.

### Claim 3 (depends on 2)

The power semiconductor device of claim 2, wherein the first type circuit element includes a transistor, and the second type circuit element includes a Schottky barrier diode.

### Claim 4 (depends on 2)

The power semiconductor device of claim 2, wherein
the first region includes a first element region and a first edge region, the first element region including the first type circuit element therein, the first edge region being between the first element region and the recessed portion, and
the second region includes a second element region and a second edge region, the second element region including the second type circuit element therein, the second edge region being, between the second element region and the recessed portion.

### Claim 5 (depends on 4)

The power semiconductor device of claim 4, wherein the source electrode is in the first element region, the metal layer is in the second element region, and the passivation layer is in contact with an upper surface of the drift layer in the first edge region and the second edge region.

### Claim 6 (depends on 4)

The power semiconductor device of claim 4, wherein
when viewed in a plan view, the recessed portion has a line shape crossing between the first region and the second region, and
a width of the recessed portion is equal to or smaller than a width of the first edge region and/or a width of the second edge region.

### Claim 7 (depends on 1)

The power semiconductor device of claim 1, wherein
a first side surface of the first region and a second side surface of the second region defined by the recessed portion face each other, and
the first side surface and the second side surface have slopes.

### Claim 8 (depends on 1)

The power semiconductor device of claim 1, wherein the source electrode and the metal layer include a same metal material.

### Claim 9 (depends on 1)

The power semiconductor device of claim 1, wherein
the power semiconductor device includes a first pad region exposing at least a portion of the source electrode from an upper surface of the passivation layer and a second pad region exposing at least a portion of the metal layer from the upper surface of the passivation layer, and
the power semiconductor device further includes a wire between the first pad region and the second pad region.

### Claim 10 (depends on 1)

The power semiconductor device of claim 1, further comprising:
a plurality of junction barrier regions in the second region, the plurality of junction barrier regions spaced apart from each other in an upper portion of the drift layer.

### Claim 11 (depends on 10)

The power semiconductor device of claim 10, wherein the plurality of junction barrier regions have a polygonal frame shape.

### Claim 12 (depends on 1)

The power semiconductor device of claim 1, wherein the first conductivity type is an N-type, and the second conductivity type is a P-type.

### Claim 13

A power semiconductor device comprising:
a first region including a transistor;
a second region spaced apart from the first region, the second region including a Schottky barrier diode;
a passivation layer on the first region and the second region; and
a third region between the first region and the second region, the third region being a region in which at least a portion of the passivation layer is removed,
wherein the first region includes,
a first SiC substrate of a first conductivity type,
a well region of a second conductivity type on the first SiC substrate,
a source region of the first conductivity type within the well region,
a gate electrode on an upper surface of the well region, and
a source electrode connected to the source region, and
the second region includes,
a second SiC substrate of the first conductivity type, and
an electrode layer connected to the second SiC substrate, and
wherein the first SiC substrate and the second SiC substrate are respective parts of an integral body.

### Claim 14 (depends on 13)

The power semiconductor device of claim 13, wherein an area of the first region is larger than an area of the second region.

### Claim 15 (depends on 13)

The power semiconductor device of claim 13, wherein
when viewed in a plan view, the first region and the second region have a same width in a first direction, and
a length of the first region is greater than a length of the second region in a second direction perpendicular to the first direction.

### Claim 16 (depends on 15)

The power semiconductor device of claim 15, wherein when viewed in a plan view, the third region has a line shape having a same width as the first region in the first direction.

### Claim 17 (depends on 13)

The power semiconductor device of claim 13, wherein the first SiC substrate and the second SiC substrate are respective parts of the integral body, and a portion of the integral body are exposed in the third region.

### Claim 18 (depends on 13)

The power semiconductor device of claim 13, wherein
the source electrode of the first region has a first separation distance from the third region, and an electrode layer of the second region has a second separation distance from the third region, and
the first separation distance is substantially equal to the second separation distance.

### Claim 19

A power semiconductor device comprising:
a substrate including SiC of a first conductivity type, the substrate including a first region and a second region;
a well region of a second conductivity type on the substrate, the well region being in the first region;
a source region of the first conductivity type within the well region;
a gate electrode on and extending along an upper surface of the well region;
a source electrode connected to the source region in the first region;
a metal layer connected to the substrate in the second region;
a passivation layer covering the source electrode and the metal layer, the passivation layer including a first pad region and a second pad region, the first pad region exposing at least a portion of the source electrode, the second pad region exposing at least a portion of the metal layer; and
a connecting member electrically connecting the source electrode exposed in the first pad region and the metal layer exposed the second pad region,
wherein the passivation layer defines a recessed portion between the first region and the second region, and the recessed portion defines a scribe lane.

### Claim 20 (depends on 19)

The power semiconductor device of claim 19, wherein the connecting member electrically connects a transistor of the first region and a Schottky barrier diode of the second region.