Semiconductor device and method of designing the same

Abstract

Without causing characteristic variations in paired elements, the increase in development cost and development period is suppressed. A plurality of MOS units 30 are arranged adjacent to each other on a main surface of a semiconductor substrate in a plan view, each of the plurality of MOS unit is comprised of at least one MOSFET and has same structure. Above the plurality of MOS units 30, a multilayer wiring layer is formed. In an uppermost wiring layer of the multilayer wiring layer, wiring M8 is formed. Each of the plurality of MOS units 3Q includes MOS unit 10 and MOS unit 20, which constitute a part of the differential circuit as paired elements. The coverage rate of MOS unit 10 covered by wiring M8 is the same as the coverage rate of MOS unit 20 covered by wiring M8 in the plan view.

Dependencies are inferred from the claim text.