# US 2026/0076172 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0076172 A1 - Document ID: US20260076172A1 - Status: Published application - Kind: A1 - Application number: 19/393,579 - Filed: 2025-11-19 - Published: 2026-03-12 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Wei-Kai Shih - Web page: https://patentgrep.com/patent/US20260076172A1 ## CPC - H10W 20/43: Layouts of interconnections - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/019: {of bond pads} - H10W 72/90: Bond pads, in general - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/29: Bond pads specially adapted therefor - H10W 74/147: {the encapsulations being multilayered} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract One of the semiconductor devices includes a semiconductor device includes a conductive pad, a passivation layer and a conductive pattern. The passivation layer surrounds the conductive pad and has a sidewall interfacing with a sidewall of the conductive pad. The conductive pattern is disposed in the passivation layer and electrically connected to the conductive pad, wherein a first surface of the conductive pattern interfacing with the passivation layer and the conductive pad has at least one turning point. ## Claims ### Claim 1 A semiconductor device, comprising: a conductive pad; a passivation layer, surrounding the conductive pad and having a sidewall interfacing with a sidewall of the conductive pad; and a conductive pattern, disposed in the passivation layer and electrically connected to the conductive pad, wherein a first surface of the conductive pattern interfacing with the passivation layer and the conductive pad has at least one turning point. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein a height of the at least one turning point is at a lower level with respect to an interface of the passivation layer and the conductive pad. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, wherein a height of the at least one turning point is lower than a height of a top of the conductive pad. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein the at least one turning point comprises a plurality of turning points at different heights. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein the passivation layer comprises a first layer and a second layer on the first layer, and a sidewall of the first layer interfacing with the conductive pattern is substantially flush with a sidewall of the second layer interfacing with the conductive pattern. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, wherein the conductive pad has a surface facing the conductive pattern, and a surface of the passivation layer is higher than the surface of the conductive pad. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, further comprising an interconnect structure, wherein the conductive pad is electrically connected to the interconnect structure. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first surface of the conductive pattern comprises a first horizontal section and an inclined section, and the conductive pad further comprises a second horizontal section interfacing with the passivation layer and a substantially vertical section between the second horizontal section and the inclined section, and the at least one turning point is disposed between the first and second horizontal sections. ### Claim 9 (depends on 8) The semiconductor device as claimed in claim 8, wherein the substantially vertical section interfaces the passivation layer. ### Claim 10 (depends on 8) The semiconductor device as claimed in claim 8, wherein the substantially vertical section interfaces the conductive pad and the passivation layer. ### Claim 11 (depends on 1) The semiconductor device as claimed in claim 1, wherein the conductive pattern is extended over a top of the passivation layer and has a second surface opposite to the first surface of the conductive pattern and substantially conformal to the first surface of the conductive pattern. ### Claim 12 (depends on 11) The semiconductor device as claimed in claim 11, wherein the second surface of the conductive pattern comprises a first horizontal section, a second horizontal section and an inclined section between the first and second horizontal sections. ### Claim 13 (depends on 1) The semiconductor device as claimed in claim 1, wherein the conductive pad has a surface facing the conductive pattern, and the passivation layer covers a portion of the surface of the conductive pad. ### Claim 14 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first surface of the conductive pattern is a concave surface. ### Claim 15 A semiconductor device, comprising: a conductive pad; a passivation layer, surrounding the conductive pad and having a sidewall interfacing with a sidewall of the conductive pad; and a conductive pattern, disposed in the passivation layer and electrically connected to the conductive pad, wherein a first surface of the conductive pattern interfacing with the passivation layer and the conductive pad has a first turning point and a second turning point disposed at different heights. ### Claim 16 (depends on 15) The semiconductor device as claimed in claim 15, wherein the heights of the first turning point and the second turning point are at a lower level with respect to an interface of the passivation layer and the conductive pad. ### Claim 17 (depends on 15) The semiconductor device as claimed in claim 15, wherein the heights of the first turning point and the second turning point are lower than a height of a top of the conductive pad. ### Claim 18 A semiconductor device, comprising: a conductive pad; a passivation layer, surrounding the conductive pad and having a sidewall interfacing with a sidewall of the conductive pad; and a conductive pattern, disposed in the passivation layer and electrically connected to the conductive pad, wherein a first surface of the conductive pattern interfacing with the passivation layer and the conductive pad has a plurality of sections connected to one another through a turning point. ### Claim 19 (depends on 18) The semiconductor device as claimed in claim 18, wherein the heights of the sections are at a lower level with respect to an interface of the passivation layer and the conductive pad. ### Claim 20 (depends on 18) The semiconductor device as claimed in claim 18, wherein the sections are lower than a height of a top of the conductive pad.