# US 2026/0076162 A1 · Split via structure for semiconductor device packaging

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- Number: US 2026/0076162 A1
- Document ID: US20260076162A1
- Status: Published application
- Kind: A1
- Application number: 19/321,715
- Filed: 2025-09-08
- Published: 2026-03-12
- Earliest claimed: 2022-08-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hong Wan Ng; Seng Kim Ye; Kelvin Tan Aik Boo; Ling Pan; See Hiong Leow
- Web page: https://patentgrep.com/patent/US20260076162A1

## CPC

- H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines}
- H05K 2201/0939: Curved pads, e.g. semi-circular or elliptical pads or lands
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.

## Claims

### Claim 1

A method of forming a semiconductor assembly, comprising:
providing a first hard mask layer on a substrate, the first hard mask layer having openings;
patterning the substrate through the hard mask layer and plating conductive material in the patterned substrate to form a first via land and a second via land on a surface of a substrate, wherein the first via land has a first footprint in a half moon shape with a first radius of curvature and the second via land has a second footprint in the half moon shape with the first radius of curvature, and wherein the first via land and the second via land are disposed entirely within a circular region having the first radius of curvature;
drilling a first hole and a second hole on the surface of the substrate, the first hole and the second hole each passing through the substrate; and
plating conductive material in the first hold and the second hole to form a first via with a second radius of curvature and a second via with the second radius of curvature, respectively, wherein the first via and the second via are respectively disposed within the first footprint and the second footprint.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
providing a second hard mask layer on the substrate, the second hard mask layer having openings, and
patterning the substrate through the second hard mask and plating conductive material in the patterned substrate to form a pair of traces including a first trace electrically coupled to the first via land and a second trace electrically coupled to the second via land.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first trace is coupled to the first via land at a first edge location of the circular region, wherein the second trace is coupled to the second via land at a second edge location of the circular region.

### Claim 4 (depends on 3)

The method of claim 3, wherein the pair of traces are a differential pair, in which the first trace and the second trace are in parallel and separated by a second gap.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first gap and the second gap have a same width, and wherein the pair of traces each has an inner edge substantially aligned with the first chord edge of the first via land and the second via land, respectively

### Claim 6 (depends on 5)

The method of claim 5, wherein the trace width of each of the pair of traces is equal to a lateral width along an axis perpendicular to the chord edge of each of the first via land and the second via land.

### Claim 7 (depends on 4)

The method of claim 4, wherein the first gap is smaller than the second gap, and the trace width of the pair of traces is smaller than a lateral width along an axis perpendicular to the chord edge of each of the first via land and the second via land.

### Claim 8 (depends on 2)

The method of claim 2, wherein the second edge location is opposite to the first edge location in the circular region.

### Claim 9 (depends on 2)

The method of claim 2, wherein trace edges of the first trace and the second trace are perpendicular to the first chord edges of the first via land and the second via land, respectively.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first via land and the second via land each has a first arcuate edge and a first chord edge.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first via and the second via each has a second arcuate edge smaller than the first arcuate edge and a second chord edge shorter than the first chord edge.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second chord edges of the first via and the second via are overlapped with the first chord edges of the first via land and the second via land, respectively.

### Claim 13

A method of forming a semiconductor device assembly, comprising:
providing a substrate;
providing a first split via on the substrate, the first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first micro via that passes through the substrate and that has a circular cross-sectional shape with a first diameter, wherein the first micro via is disposed within the first footprint; and
forming a second split via on the substrate, the second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second micro via that passes through the substrate and that has the circular cross-sectional shape with the first diameter, wherein the second micro via is disposed within the second footprint,
wherein the first via land and the second via land are disposed entirely within a circular region having the first radius of curvature.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming a pair of traces including a first trace electrically coupled to the first via land with a trace width at a first edge location of the circular region and a second trace electrically coupled to the second via land with the trace width at a second edge location of the circular region, wherein the first via land and the second via land each has a first arcuate arc edge and a chord edge.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first via land and the second via land are symmetric in the circular region and isolated by a first gap, and wherein the pair of traces are a differential pair, in which the first trace and the second trace are in parallel and separated by a second gap.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first gap and the second gap have a same width, wherein the pair of traces each has an inner edge substantially aligned with the first chord edge of the first via land and the second via land, respectively, and wherein the trace width of each of the pair of traces is equal to a lateral width along an axis perpendicular to the chord edge of each of the first via land and the second via land.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first gap is smaller than the second gap, and the trace width of the pair of traces is smaller than a lateral width along an axis perpendicular to the chord edge of each of the first via land and the second via land.

### Claim 18 (depends on 14)

The method of claim 14, wherein the second edge location is opposite to the first edge location in the circular region, and wherein trace edges of the first trace and the second trace are perpendicular to the first chord edges of the first via land and the second via land, respectively.

### Claim 19

A method of forming a semiconductor device assembly, comprising:
providing a substrate;
forming a first via land on a surface of the substrate, the first via land having a first footprint with a half-moon shape with a first radius of curvature;
forming a second via land on a surface of the substrate, the second via land having a second footprint with a half-moon shape with the first radius of curvature;
forming a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is vertically aligned with and electrically coupled to the first via land; and
forming a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is vertically aligned with and electrically coupled to the second via land,
wherein the first via land and the second via land are reflectively symmetric and isolated by a first gap.

### Claim 20 (depends on 19)

The method of claim 19, further comprising forming a pair of traces including a first trace electrically coupled to the first via land with a trace width at a first edge location of the first via land and a second trace electrically coupled to the second via land with the trace width at a second edge location of the second via land, wherein the first via land and the second via land each has a first arcuate arc edge and a chord edge.