# US 2026/0076159 A1 · Managing isolating structures in semiconductor devices

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- Number: US 2026/0076159 A1
- Document ID: US20260076159A1
- Status: Published application
- Kind: A1
- Application number: 18/931,517
- Filed: 2024-10-30
- Published: 2026-03-12
- Earliest claimed: 2024-09-10
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Jianlan WEI; Zongliang HUO; Chao YAN; Jing GAO; Sizhe LI; Xiaoming MAO; Tingting ZHAO
- Web page: https://patentgrep.com/patent/US20260076159A1

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10B 41/10: characterised by the top-view layout
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/30: characterised by the memory core region
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/30: characterised by the memory core region
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure relates to methods, devices, and systems for managing isolating structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction. The semiconductor device further includes a gate line slit structure extending through the first stack along the second direction, and a first isolating structure extending along the first direction. The first isolating structure includes a first portion in the first stack and a second portion in the gate line slit structure. A size of the first portion is greater than a size of the second portion along the second direction.

## Claims

### Claim 1

A semiconductor device, comprising:
a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction;
a gate line slit structure extending through the first stack along the second direction; and
a first isolating structure extending along the first direction, wherein the first isolating structure comprises a first portion in the first stack and a second portion in the gate line slit structure, wherein a size of the first portion is greater than a size of the second portion along the second direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the size of the first portion is greater than a size of an isolating layer of the first stack along the second direction.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first isolating structure is between two conductive layers of the first stack.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second stack of conductive layers and isolating layers extending along the first direction and alternating with each other along the second direction, wherein the second stack is adjacent to the first stack along the second direction; and
a second isolating structure extending along the first direction between the first stack and the second stack.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first isolating structure comprises a dielectric material or a semiconductor material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the gate line slit structure penetrates through the second portion of the first isolating structure, and
wherein the portion of the gate line slit structure comprises a plurality of cylinders that are arranged along a third direction perpendicular to the first direction and the second direction.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the portion of the gate line slit structure further comprises a structure having a surface that comprises a series of curves.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a surface of the gate line slit structure comprises a series of curves.

### Claim 9

A semiconductor device, comprising:
a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction;
channel structures extending through the first stack along the second direction;
a gate line slit structure extending through the first stack along the second direction; and
a first isolating structure extending along the first direction, wherein the first isolating structure comprises a first portion in the first stack and a second portion in the gate line slit structure,
wherein a first portion of the gate line slit structure is above the first isolating structure along the second direction, wherein a size of the first portion of the gate line slit structure is greater than a size of one of the channel structures along the first direction.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a second portion of the gate line slit structure penetrates through the first isolating structure, wherein a size of the second portion of the gate line slit structure is greater than the size of the one of the channel structures along the first direction.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first isolating structure is between two conductive layers of the first stack.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising:
a second stack of conductive layers and isolating layers extending along the first direction and alternating with each other along the second direction, wherein the second stack is adjacent to the first stack along the second direction; and
a second isolating structure extending along the first direction between the first stack and the second stack.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the first isolating structure comprises a dielectric material or a semiconductor material.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the second portion of the gate line slit structure comprises a plurality of cylinders that are arranged along a third direction perpendicular to the first direction and the second direction.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second portion of the gate line slit structure further comprises a structure having a surface that comprises a series of curves.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein a surface of the first portion of the gate line slit structure comprises a series of curves.

### Claim 17

A method of forming a semiconductor device, comprising:
forming a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction;
forming a gate line slit structure extending through the first stack along the second direction; and
forming an isolating structure extending along the first direction, wherein the isolating structure comprises a first portion in the first stack and a second portion in the gate line slit structure, wherein a size of the first portion is greater than a size of the second portion along the second direction.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a stack of dielectric layers and isolating layers alternating with each other along the second direction, wherein a size of a first isolating layer of the isolating layers is greater than a size of a second isolating layer of the isolating layers along the second direction;
forming gate line holes extending through the stack of dielectric layers and isolating layers, wherein the gate line holes are arranged along a third direction perpendicular to the first direction and the second direction; and
forming a gate line space by expanding the gate line holes, wherein the gate line holes in the second isolating layer are connected with each other along the third direction to form the gate line space, and wherein at least a portion of the gate line holes in the first isolating layer are separate from each other.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming the first stack of conductive layers and isolating layers comprises replacing the dielectric layers of the stack with conductive layers, and
wherein forming the gate line slit structure comprises filling the gate line space with a semiconductor material.

### Claim 20 (depends on 18)

The method of claim 18, wherein the isolating structure comprises a remaining portion of the first isolating layer after expanding the gate line holes.