# US 2026/0076104 A1 · Non-volatile memory device and manufacturing technology

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- Number: US 2026/0076104 A1
- Document ID: US20260076104A1
- Status: Published application
- Kind: A1
- Application number: 19/387,748
- Filed: 2025-11-13
- Published: 2026-03-12
- Earliest claimed: 2020-05-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chern-Yow Hsu; Chung-Chiang Min; Shih-Chang Liu
- Web page: https://patentgrep.com/patent/US20260076104A1

## CPC

- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/801: {Constructional details of multistable switching devices}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device with hard mask insulator and its manufacturing methods are provided. In some embodiments, a first conductive layer, a resistance switching dielectric layer, and a second conductive layer are formed over a substrate. Then a first metal layer, an insulating layer, and a second metal layer are deposited over the second conductive layer. A series of etch is performed to pattern the second metal layer, the second insulating layer, and the first metal layer to form a hard mask. The second conductive layer and the resistance switching dielectric layer are etched according to the hard mask to form a top electrode and a resistance switching dielectric for a memory cell.

## Claims

### Claim 1

A method, comprising:
forming a first conductive layer, a resistance switching dielectric layer over the first conductive layer, and a second conductive layer over the resistance switching dielectric layer;
depositing a first metal layer over the second conductive layer;
depositing an insulating layer over the first metal layer;
depositing a second metal layer over the second insulating layer; and
performing a series of etch to pattern the second metal layer, the second insulating layer, and the first metal layer to form a hard mask;
etching the second conductive layer and the resistance switching dielectric layer according to the hard mask to form a top electrode and a resistance switching dielectric for a memory cell.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second conductive layer is made of tungsten and the first metal layer is made of tantalum nitride.

### Claim 3 (depends on 1)

The method of claim 1, wherein the insulating layer is made of silicon dioxide, silicon nitride, silicon carbide, or the combination thereof.

### Claim 4 (depends on 1)

The method of claim 1, further comprising depositing and patterning an additional insulating layer to form a masking insulator between the second conductive layer and the first metal layer.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a dielectric spacer layer over the first conductive layer, extending alongside the resistance switching dielectric and the top electrode, and further extending over the masking insulator.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
performing a first etch to the dielectric spacer layer to form a sidewall spacer alongside the resistance switching dielectric, the top electrode, and the hard mask; and
performing a second etch to pattern the first conductive layer according to the hard mask and the sidewall spacer to form a bottom electrode, wherein the bottom electrode has a sidewall aligned with that of the sidewall spacer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
forming an etch stop layer alongside the bottom electrode, the sidewall spacer, and further extending over the hard mask;
forming an upper dielectric layer over and surrounding the etch stop layer; and
forming a conductive via extending through the upper dielectric layer and the hard mask to reach on the top electrode.

### Claim 8 (depends on 5)

The method of claim 5, wherein the dielectric spacer layer is formed directly on the first conductive layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second metal layer is made of tantalum.

### Claim 10 (depends on 1)

The method of claim 1, further comprising: prior to performing the series of etch, forming a first dielectric masking layer directly on the second metal layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising: prior to performing the series of etch, forming an amorphous carbon film over the first dielectric masking layer and a second dielectric masking layer over the amorphous carbon film.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second dielectric masking layer and the amorphous carbon film are removed after patterning the second conductive layer.

### Claim 13 (depends on 1)

The method of claim 1, wherein the second metal layer and the insulating layer are removed after forming the resistance switching dielectric.

### Claim 14 (depends on 1)

The method of claim 1, wherein the insulating layer has a thickness in a range of from about 3 nm to about 10 nm.

### Claim 15

A method, comprising:
forming a memory cell stack over a substrate, the memory cell stack comprising a first conductive layer, a resistance switching dielectric layer over the first conductive layer, a second conductive layer over the resistance switching dielectric layer;
forming a hard masking stack over the memory cell stack, wherein the hard masking stack comprises a first insulating layer at bottom contacting the second conductive layer and a first metal layer and a second metal layer disposed over the first insulating layer and separated from one another by a second insulating layer;
performing a series of etch to the hard masking stack to form a hard mask; and
according to the hard mask, patterning the second conductive layer and the resistance switching dielectric layer to form a top electrode and a resistance switching dielectric.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a sidewall spacer over the substrate, extending upwardly alongside sidewalls of the resistance switching dielectric, the top electrode, and the hard mask; and
forming an etch stop layer directly on and conformally lining the sidewall spacer and an upper surface of the hard mask.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
forming an upper dielectric layer over and surrounding the etch stop layer; and
performing an etch through the upper dielectric layer and the hard mask to form a via opening; and
filling the via opening with a conductive material to form a conductive via having a sidewall contacting the hard mask and the etch stop layer.

### Claim 18

A method for manufacturing a memory cell, the method comprising:
depositing and patterning a first conductive layer over a substrate, a resistance switching dielectric layer over the first conductive layer, and a second conductive layer over the resistance switching dielectric layer;
depositing and patterning a masking stack directly on the second conductive layer, the masking stack including a first metal layer and a second metal layer separated from one another by an insulating layer; and
forming a conductive via through the masking stack reaching an upper surface of the second conductive layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
forming a sidewall spacer extending upwardly along sidewalls of the patterned resistance switching dielectric layer, the second conductive layer, and the masking stack; and
forming an etch stop layer conformally lining the sidewall spacer;
wherein the sidewall spacer and the etch stop layer are made of silicon nitride or silicon carbide.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
forming a word line transistor over the substrate;
forming a lower metal line surrounded that connects the word line transistor with the first conductive layer through a first conductive via; and
forming an upper metal line that is coupled to the second conductive layer through the conductive via.