# US 2026/0075889 A1 · Hybrid isolation pillars

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- Number: US 2026/0075889 A1
- Document ID: US20260075889A1
- Status: Published application
- Kind: A1
- Application number: 18/828,659
- Filed: 2024-09-09
- Published: 2026-03-12
- Earliest claimed: 2024-09-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Susan Ng Emans; Ruilong Xie; Julien Frougier; HUIMEI ZHOU; Ravikumar Ramachandran; Kisik Choi; Effendi Leobandung
- Web page: https://patentgrep.com/patent/US20260075889A1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor IC device includes a hybrid isolation pillar that has a first isolation pillar and a second isolation pillar. The semiconductor IC device includes a source/drain region in direct contact with the first isolation pillar and in direct contact with the second isolation pillar. The first isolation pillar may be composed of a same or different material relative to the material of the second isolation pillar. The source/drain region may be confined by the first isolation pillar and the second isolation pillar. The hybrid isolation pillar may reduce parasitic capacitance and may reduce a pitch between a n-type transistor and a p-type transistor and may reduce a pitch between the same type transistors within a transistor cell.

## Claims

### Claim 1

A semiconductor integrated circuit (IC) device comprising:
a first isolation pillar and a second isolation pillar; and
a source/drain region in direct contact with the first isolation pillar and in direct contact with the second isolation pillar.

### Claim 2 (depends on 1)

The semiconductor IC device of claim 1, wherein a top surface of the first isolation pillar is above a top surface of the second isolation pillar.

### Claim 3 (depends on 2)

The semiconductor IC device of claim 2, wherein a bottom surface of the first isolation pillar is below a bottom surface of the second isolation pillar.

### Claim 4 (depends on 3)

The semiconductor IC device of claim 3, further comprising:
a plurality of nanosheet channels each in direct contact with the source/drain region and each in direct contact first isolation pillar.

### Claim 5 (depends on 4)

The semiconductor IC device of claim 4, further comprising:
a gate structure in direct contact with the plurality of nanosheet channels, in direct contact with the first isolation pillar, and in direct contact with the second isolation pillar.

### Claim 6 (depends on 5)

The semiconductor IC device of claim 5, wherein the top surface of the first isolation pillar is substantially coplanar with a top surface of the gate structure.

### Claim 7 (depends on 6)

The semiconductor IC device of claim 6, further comprising:
a shallow trench isolation (STI) region below the second isolation pillar.

### Claim 8 (depends on 7)

The semiconductor IC device of claim 7, further comprising:
a backside contact in direct contact with the source/drain region, in direct contact with the first isolation pillar, and in direct contact with the STI region.

### Claim 9 (depends on 1)

The semiconductor IC device of claim 1, wherein the first isolation pillar is composed of a first dielectric material and wherein the second isolation pillar is composed of a second dielectric material that is different than the first dielectric material.

### Claim 10

A semiconductor integrated circuit (IC) device comprising:
a first transistor comprising a first source/drain region and a plurality of first nanosheet channels;
a second transistor comprising a second source/drain region;
a first isolation pillar in direct contact with the first source/drain region and in direct contact with each of the plurality of first nanosheet channels; and
a second isolation pillar in direct contact with the first source/drain region and in direct contact with the second source/drain region.

### Claim 11 (depends on 10)

The semiconductor IC device of claim 10, wherein a top surface of the first isolation pillar is above a top surface of the second isolation pillar.

### Claim 12 (depends on 11)

The semiconductor IC device of claim 11, wherein a bottom surface of the first isolation pillar is below a bottom surface of the second isolation pillar.

### Claim 13 (depends on 12)

The semiconductor IC device of claim 12, further comprising:
a plurality of second nanosheet channels each in direct contact with the second source/drain region.

### Claim 14 (depends on 13)

The semiconductor IC device of claim 13, further comprising:
a gate structure in direct contact with the plurality of first nanosheet channels, in direct contact with the plurality of second nanosheet channels, in direct contact with the first isolation pillar, and in direct contact with the second isolation pillar.

### Claim 15 (depends on 14)

The semiconductor IC device of claim 14, wherein the top surface of the first isolation pillar is substantially coplanar with a top surface of the gate structure.

### Claim 16 (depends on 15)

The semiconductor IC device of claim 15, further comprising:
a shallow trench isolation (STI) region below the second isolation pillar.

### Claim 17 (depends on 16)

The semiconductor IC device of claim 16, further comprising:
a first backside contact in direct contact with the first source/drain region, in direct contact with the first isolation pillar, and in direct contact with the STI region.

### Claim 18 (depends on 10)

The semiconductor IC device of claim 10, wherein the first isolation pillar is composed of a first dielectric material and wherein the second isolation pillar is composed of a second dielectric material that is different than the first dielectric material.

### Claim 19

A semiconductor integrated circuit (IC) device comprising:
a first source/drain region;
a second source/drain region;
a first isolation pillar in direct contact with a first sidewall of the first source/drain region;
a second isolation pillar in direct contact with a second sidewall of the first source/drain region and in direct contact with a first sidewall of the second source/drain region; and
a third isolation pillar in direct contact with a second sidewall of the second source/drain region.

### Claim 20 (depends on 19)

The semiconductor IC device of claim 19, wherein a bottom surface of the first isolation pillar is below a bottom surface of the second isolation pillar and wherein the bottom surface of the first isolation pillar is substantially coplanar with a bottom surface of the third isolation pillar.