# US 2026/0075868 A1 · Semiconductor device including air gap

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- Number: US 2026/0075868 A1
- Document ID: US20260075868A1
- Status: Published application
- Kind: A1
- Application number: 19/390,051
- Filed: 2025-11-14
- Published: 2026-03-12
- Earliest claimed: 2021-10-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sooyeon HONG; Deokhan BAE; Juhun PARK; Yuri LEE; Yoonyoung JUNG
- Web page: https://patentgrep.com/patent/US20260075868A1

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/01: Manufacture or treatment
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming an active pattern extending in a first direction in a substrate;
forming first and second sacrificial gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction in the substrate, and forming gate spacers on sidewalls of each of the first and second sacrificial gate structures;
forming source/drain regions by recessing portions of the active pattern exposed on both sides of the first and second sacrificial gate structures and the gate spacers;
forming an interlayer insulating layer covering the gate spacers and the source/drain regions;
removing the first and second sacrificial gate structures;
forming first and second gate structures respectively including a gate insulating layer on inner sidewalls of the gate spacers and a gate electrode on the gate insulating layer;
forming a first sacrificial interlayer insulating layer over the interlayer insulating layer and the first and second gate structures;
forming first, second, and third contact structures spaced apart from each other in the first direction and penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to contact the respective source/drain regions;
forming a second sacrificial interlayer insulating layer over the first sacrificial interlayer insulating layer and the first, second, and third contact structures;
forming a mask pattern on the second sacrificial interlayer insulating layer, the mask pattern having an opening overlapping the first and second gate structures and the second contact structure in a vertical direction;
forming a recess region by etching the first and second sacrificial interlayer insulating layers using the mask pattern to expose portions of sidewalls of the second contact structure and sidewalls of the first and second gate structures adjacent thereto; and
forming a contact insulating layer in the recess region.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, wherein the mask pattern overlaps the first and third contact structures in the vertical direction.

### Claim 3 (depends on 1)

The manufacturing method of claim 1, wherein forming each of the first and second gate structures comprises:
forming an insulating layer over a gate insulating layer, a gate electrode, and an interlayer insulating layer; and
removing the insulating layer such that an upper surface of the interlayer insulating layer is exposed so as to form a gate capping layer.

### Claim 4 (depends on 3)

The manufacturing method of claim 3, wherein an upper surface of the gate capping layer is coplanar with an upper surface of the contact insulating layer.

### Claim 5 (depends on 1)

The manufacturing method of claim 1, wherein forming the first, second, and third contact structures comprises:
forming contact holes penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to expose the source/drain regions; and
sequentially forming a barrier layer and an embedded conductive layer in each of the contact holes.

### Claim 6 (depends on 1)

The manufacturing method of claim 1, wherein forming the contact insulating layer comprises:
forming a preliminary contact insulating layer covering the mask pattern; and
removing the preliminary contact insulating layer such that upper surfaces of the first and second gate structures are exposed.

### Claim 7 (depends on 1)

The manufacturing method of claim 1, further comprising removing the first and second sacrificial interlayer insulating layers to expose upper surfaces of the first and second gate structures, upper surfaces of the first and third contact structures, and an upper surface of the contact insulating layer.

### Claim 8 (depends on 7)

The manufacturing method of claim 7, further comprising:
forming an upper interlayer insulating layer over the first and second gate structures, the first and third contact structures, and the contact insulating layer; and
forming a wiring structure penetrating the upper interlayer insulating layer to be connected to the first contact structure,
wherein the second contact structure vertically overlaps the upper interlayer insulating layer.

### Claim 9 (depends on 1)

The manufacturing method of claim 1, wherein an upper surface of the contact insulating layer is coplanar with upper surfaces of the first and third contact structures.

### Claim 10 (depends on 1)

The manufacturing method of claim 1, wherein the mask pattern overlaps the first and third contact structures in the vertical direction.

### Claim 11 (depends on 1)

The manufacturing method of claim 1,
wherein the recess region comprises an upper region exposing the first and second sacrificial interlayer insulating layers and a lower region extending from the upper region to expose portions of sidewalls of the second contact structure and portions of sidewalls of the first and second gate structures, and
wherein a width of the upper region in the first direction is greater than a width of the lower region in the first direction.

### Claim 12 (depends on 1)

The manufacturing method of claim 1, wherein the contact insulating layer comprises at least one air gap.

### Claim 13

A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming an active pattern extending in a first direction in a substrate;
forming first and second sacrificial gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction in the substrate, and forming gate spacers on sidewalls of each of the first and second sacrificial gate structures;
forming a source/drain region by recessing the active pattern exposed on both sides of the gate spacers between the first and second sacrificial gate structures;
forming an interlayer insulating layer covering the gate spacers and the source/drain region;
removing the first and second sacrificial gate structures and forming first and second gate structures respectively including a gate insulating layer, a gate electrode on the gate insulating layer, and a gate capping layer on the gate spacers, the gate insulating layer, and the gate electrode;
forming a first sacrificial interlayer insulating layer over the interlayer insulating layer and the first and second gate structures;
forming a preliminary contact structure penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to contact the source/drain region;
etching the preliminary contact structure in a vertical direction to form a contact structure having an upper surface at a level lower than the first and second gate structures; and
forming a contact insulating layer contacting portions of sidewalls of the first and second gate structures exposed from the contact structure.

### Claim 14 (depends on 13)

The manufacturing method of claim 13, further comprising:
removing the first sacrificial interlayer insulating layer such that upper surfaces of the first and second gate structures are exposed; and
forming an upper interlayer insulating layer over the first and second gate structures and the contact insulating layer.

### Claim 15 (depends on 14)

The manufacturing method of claim 14,
wherein the interlayer insulating layer further comprises an air gap being in contact with the upper interlayer insulating layer.

### Claim 16 (depends on 13)

The manufacturing method of claim 13,
wherein the contact structure includes a barrier layer and an embedded conductive layer on the barrier layer, and
wherein an upper surface of the embedded conductive layer is curved.

### Claim 17 (depends on 13)

The manufacturing method of claim 13, further comprising forming a gate contact penetrating the gate capping layer to be connected to the gate electrode.

### Claim 18

A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming an active pattern extending in a first direction in a substrate;
forming first and second gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction, each of the first and second gate structures including a gate electrode, gate spacers on both sides of the gate electrode, and a gate capping layer on the gate electrode and the gate spacers;
recessing portions of the active pattern exposed on both sides of the gate spacers to form first to third source/drain regions spaced apart from each other in the first direction;
forming an interlayer insulating layer covering the first to third source/drain regions;
forming first to third contact structures spaced apart from each other in the first direction and penetrating the interlayer insulating layer to contact the respective first to third source/drain regions;
etching the second contact structure in a vertical direction to form a recess region exposing an upper surface of the etched second contact structure and sidewalls of the first and second gate structures facing each other across the second contact structure; and
forming a contact insulating layer in the recess region,
wherein upper surfaces of the first and third contact structures are coplanar with upper surfaces of the first and second gate structures and an upper surface of the contact insulating layer.

### Claim 19 (depends on 18)

The manufacturing method of claim 18,
wherein the contact insulating layer comprises at least one air gap.

### Claim 20 (depends on 18)

The manufacturing method of claim 18,
wherein the second contact structure includes a contact barrier layer and a contact plug on the contact barrier layer, and
wherein an upper end of the contact plug is at a level higher than an upper end of the contact barrier layer.