# US 2026/0075845 A1 · Microelectronic devices with tier stacks with varied tier thicknesses, and related methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0075845 A1 - Document ID: US20260075845A1 - Status: Published application - Kind: A1 - Application number: 19/385,993 - Filed: 2025-11-11 - Published: 2026-03-12 - Earliest claimed: 2020-06-17 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: John D. Hopkins; Nancy M. Lomeli - Web page: https://patentgrep.com/patent/US20260075845A1 ## CPC - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed. ## Claims ### Claim 1 A microelectronic device, comprising: a stack structure comprising insulative structures and conductive structures arranged in tiers, the tiers arranged in a vertically repeated pattern, the tiers individually comprising at least one of the insulative structures and at least one of the conductive structures, at least some of the conductive structures providing word lines vertically spaced from one another by at least one of the insulative structures, the insulative structures in some elevations of the stack structure being thicker than the insulative structures in some other elevations of the stack structure. ### Claim 2 (depends on 1) The microelectronic device of claim 1, wherein the conductive structures providing word lines within the some elevations of the stack structure are substantially as thick as the conductive structures providing word lines within the some other elevations of the stack structure. ### Claim 3 (depends on 1) The microelectronic device of claim 1, wherein the conductive structures providing word lines with the some elevations of the stack structure are thicker than the conductive structures providing word lines within the some other elevations of the stack structure. ### Claim 4 (depends on 1) The microelectronic device of claim 1, further comprising features extending substantially vertically through a height of the stack structure, including through the some elevations of the stack structure and through the some other elevations of the stack structure, the features tapering in lateral width through the height of the stack structure. ### Claim 5 (depends on 4) The microelectronic device of claim 4, wherein the features are narrower in lateral width through the some elevations of the stack structure than through the some other elevations of the stack structure. ### Claim 6 (depends on 4) The microelectronic device of claim 4, wherein the features are configured as conductive contacts. ### Claim 7 (depends on 4) The microelectronic device of claim 4, wherein the features are configured as pillars along which extend at least one vertical string of memory cells. ### Claim 8 (depends on 1) The microelectronic device of claim 1, wherein the stack structure comprises multiple decks individually comprising the insulative structures and the conductive structures arranged in the tiers. ### Claim 9 (depends on 1) The microelectronic device of claim 1, wherein the conductive structures individually comprise at least one conductive material within a liner comprising at least one other conductive material. ### Claim 10 (depends on 1) The microelectronic device of claim 1, wherein the some elevations are vertically below the some other elevations of the stack structure. ### Claim 11 A microelectronic device, comprising: decks individually comprising a stack structure having insulative structures and conductive structures arranged in a vertically repeated tier pattern, within individual of the decks, a vertical height of a lowest of the insulative structures being greater than a vertical height of a highest of the insulative structures. ### Claim 12 (depends on 11) The microelectronic device of claim 11, wherein, within individual of the decks, a vertical height of the conductive structures being substantially equal to one another throughout the individual of the decks. ### Claim 13 (depends on 11) The microelectronic device of claim 11, wherein, within individual of the decks, a vertical height of a lowest of the conductive structures being greater than a vertical height of a highest of the conductive structures. ### Claim 14 (depends on 11) The microelectronic device of claim 11, wherein the conductive structures are configured as word lines. ### Claim 15 (depends on 11) The microelectronic device of claim 11, wherein the vertically repeated tier pattern consists of a single one of the insulative structures and a single one of the conductive structures. ### Claim 16 A microelectronic device, comprising: a stack structure comprising insulative structures and conductive word line structures arranged in tiers, the tiers arranged in a vertically repeated pattern, the tiers individually comprising at least one of the insulative structures and at least one of the conductive word line structures, the insulative structures individually defining an insulative structure height, the insulative structure height being greater within some elevations of the stack structure than within some other elevations of the stack structure. ### Claim 17 (depends on 16) The microelectronic device of claim 16, wherein the conductive word line structures individually define a conductive structure height, the conductive structure height being substantially consistent within the some elevations of the stack structure as within the some other elevations of the stack structure. ### Claim 18 (depends on 16) The microelectronic device of claim 16, wherein the conductive word line structures individually define a conductive structure height, the conductive structure height being greater within the some elevations of the stack structure than within the some other elevations of the stack structure. ### Claim 19 (depends on 16) The microelectronic device of claim 16, wherein the insulative structures include cantilever portions adjacent fill material structures. ### Claim 20 (depends on 19) The microelectronic device of claim 19, wherein the cantilever portions are horizontally wider for the insulative structures having a greater insulative structure height than for the insulative structures having a lesser insulative structure height.