Controlling trap formation to improve memory window in one-time prograrm devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Yu-Kuan Lin, Shih-Hao Lin
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Abstract
In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
Claims20
A semiconductor structure, comprising:
- a read transistor over a substrate, and comprising a read gate electrode and a read dielectric layer between the read gate electrode and the substrate;
- and
- a program transistor over the substrate and electrically coupled in series with the read transistor, and comprising a pair of source/drain regions in the substrate, a program gate electrode between the pair of source/drain regions, and a program dielectric layer between the program gate electrode and the substrate;
- wherein the program dielectric layer has a first portion and a second portion that underlie the program gate electrode and that entirely and respectively overlie the pair of source/drain regions, and wherein the first and second portions of the program dielectric layer have individual concentrations of defects greater than a concentration of defects of the read dielectric layer.
A semiconductor structure, comprising:
- a semiconductor substrate;
- a read dielectric layer overlying the semiconductor substrate;
- a read gate electrode overlying the read dielectric layer;
- a program dielectric layer overlying the semiconductor substrate;
- a program gate electrode overlying the program dielectric layer;
- and
- a source/drain region in the semiconductor substrate, between and bordering the read and program gate electrodes;
- wherein a bottom surface of the read gate electrode has a first average surface roughness at an elevation over the semiconductor substrate, wherein a bottom surface of the program gate electrode has a first portion and a second portion that are at opposite sidewalls of the program gate electrode and that have a second average surface roughness at the elevation, and wherein the second average surface roughness is greater than the first average surface roughness.
A semiconductor structure, comprising:
- a semiconductor substrate;
- a read dielectric layer overlying the semiconductor substrate;
- a read gate electrode overlying the read dielectric layer;
- a program dielectric layer overlying the semiconductor substrate;
- a program gate electrode overlying the program dielectric layer;
- and
- a source/drain region in the semiconductor substrate, between and bordering the read and program gate electrodes;
- wherein the program dielectric layer has a first portion and a second portion with individual breakdown voltages less than a breakdown voltage of the read dielectric layer, and wherein the first and second portions of the program dielectric layer have the same thickness as the read dielectric layer and are on opposite sides of the program gate electrode.
Dependencies are inferred from the claim text.