# US 2026/0075801 A1 · Memory device and method for manufacturing the same

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- Number: US 2026/0075801 A1
- Document ID: US20260075801A1
- Status: Published application
- Kind: A1
- Application number: 19/319,366
- Filed: 2025-09-04
- Published: 2026-03-12
- Earliest claimed: 2024-09-06
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Chien-Liang WU; Yi-Hao CHIEN
- Web page: https://patentgrep.com/patent/US20260075801A1

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10B 12/50: {Peripheral circuit region structures}
- H10P 30/209: {in silicon to make buried insulating layers}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a memory device includes providing a substrate, an array region of the substrate includes a central region and an edge region surrounding the central region, and the substrate includes a first active region and a second active region separated by an isolation structure. The method includes sequentially forming a bit line contact and a bit line structure over the first active region, conformally forming a dielectric liner on the substrate to cover the bit line contact and the bit line structure, and performing an etching process on the substrate to form a trench and expose the second active region. The method further includes performing an ion implantation process on the trench in the edge region to form an insulating layer at a bottom of the trench and covering the second active region, and forming a capacitor contact structure over the second active region.

## Claims

### Claim 1

A method for manufacturing a memory device, comprising:
providing a substrate, wherein an array region of the substrate comprises a central region and a boundary region surrounding the central region, and wherein the substrate comprises a first active region and a second active region separated by an isolation structure;
sequentially forming a bit line contact and a bit line structure over the first active region of the substrate;
conformally forming a dielectric liner on the substrate to cover sidewalls of the bit line contact and the bit line structure and a top surface of the bit line structure;
performing an etching process on the substrate to form a trench and expose the second active region;
performing an ion implantation process in the trench located in the boundary region of the substrate to form an insulating layer at a bottom of the trench and covering the second active region; and
forming a capacitor contact structure over the second active region.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein an element used in the ion implantation process is selected from xenon (Xe), krypton (Kr), iron (Fe), argon (Ar), or nitrogen (N).

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the second active region located in the boundary region is electrically isolated from the capacitor contact structure by the insulating layer.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the insulating layer is formed at the bottom of the trench and is embedded in the substrate.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein a level of a lowest surface of the insulating layer is positioned above a level of a top surface of the first active region.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein performing the ion implantation process further comprises:
forming a patterned mask to cover the central region of the array region of the substrate and expose the boundary region of the array region of the substrate;
performing the ion implantation process; and
removing the patterned mask.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein the capacitor contact structure comprises, from bottom to top, a first conductive layer, a silicide layer, and a second conductive layer.

### Claim 8 (depends on 7)

The method as claimed in claim 7, wherein the silicide layer comprises tungsten silicide (WSi) or cobalt silicide (CoSi).

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein the bit line structure comprises a multi-layer stack including a plurality of conductive layers and at least one dielectric layer and a cap layer.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the plurality of conductive layers comprise tungsten (W), titanium (Ti), titanium nitride (TiN), or a combination thereof.

### Claim 11 (depends on 1)

The method as claimed in claim 1, wherein forming the dielectric liner comprises depositing a plurality of dielectric layers, and wherein the plurality of dielectric layers comprise at least a nitride material and an oxide material.

### Claim 12 (depends on 1)

The method as claimed in claim 1, wherein the dielectric liner comprises a conformally deposited first spacer material layer and at least one subsequently deposited filling spacer material layer.

### Claim 13 (depends on 1)

The method as claimed in claim 1, wherein the etching process is an anisotropic etching process selected from reactive ion etching, plasma etching, inductively coupled plasma etching, or a combination thereof.

### Claim 14 (depends on 1)

The method as claimed in claim 1, wherein the dielectric liner electrically isolates the capacitor contact structure formed over the second active region from the bit line contact disposed over the first active region.

### Claim 15

A memory device, comprising:
a substrate, wherein an array region of the substrate comprises a central region and a boundary region surrounding the central region, and wherein the substrate comprises a first active region and a second active region separated by an isolation structure;
a bit line structure disposed over the first active region of the substrate;
a trench disposed over the second active region of the substrate;
an insulating layer located at a bottom of the trench and covering the second active region; and
a capacitor contact structure disposed over the second active region and filled into the trench.

### Claim 16 (depends on 15)

The memory device as claimed in claim 15, wherein the insulating layer comprises ions implanted from an element selected from xenon (Xe), krypton (Kr), iron (Fe), argon (Ar), and nitrogen (N).

### Claim 17 (depends on 15)

The memory device as claimed in claim 15, wherein the second active region located in the boundary region is electrically isolated from the capacitor contact structure by the insulating layer.

### Claim 18 (depends on 15)

The memory device as claimed in claim 15, wherein a level of a lowest surface of the insulating layer is higher than a level of a top surface of the first active region.

### Claim 19 (depends on 15)

The memory device as claimed in claim 15, wherein the insulating layer is formed at the bottom of the trench and is at least partially embedded within the substrate.

### Claim 20 (depends on 15)

The memory device as claimed in claim 15, wherein the capacitor contact structure is spaced apart from the bit line structure by the dielectric liner.