US 2026/0075798 A1 · Memory Circuitry And Methods Used In Forming Memory Circuitry

Abstract

A method includes forming pillars that project upwardly from a substrate and comprise conductively-doped monocrystalline semiconductive material. The pillars comprise either one source/drain region or another source/drain region of a transistor of individual memory cells of the memory circuitry being formed. Conductively-doped monocrystalline semiconductor material is grown from a top and sidewalls of the pillars to form conductive monocrystalline coverings that are individually directly above the top and circumferentially about the sidewalls of the individual pillars. Digitlines are formed that are individually above and directly electrically coupled to a plurality of the individual pillars of the another source/drain regions through the epitaxially-grown conductive monocrystalline covering that is directly there-above. Storage elements are formed to be above and electrically coupled to the individual pillars of the one source/drain regions through the epitaxially-grown conductive monocrystalline covering that is directly there-above. Structures are disclosed.

Claims22

Dependent claims

A method used in forming memory circuitry, comprising:

forming pillars that project upwardly from a substrate and comprise conductively-doped monocrystalline semiconductive material, individual of the pillars comprising either one source/drain region or another source/drain region of a transistor of individual memory cells of the memory circuitry being formed;
epitaxially growing conductively-doped monocrystalline semiconductor material from a top and sidewalls of the individual pillars to form conductive monocrystalline coverings that are individually directly above the top and circumferentially about the sidewalls of the individual pillars;
forming digitlines that are individually above and directly electrically coupled to a plurality of the individual pillars of the another source/drain regions through the epitaxially-grown conductive monocrystalline covering that is directly there-above;
and
forming storage elements of the individual memory cells, the storage elements individually being above and electrically coupled to the individual pillars of the one source/drain regions through the epitaxially-grown conductive monocrystalline covering that is directly there-above.

2 more elements

Memory circuitry comprising:

transistors individually comprising:
one source/drain region and another source/drain region, the one and another source/drain regions individually comprising a pillar comprising conductively-doped monocrystalline semiconductive material, the pillar comprising a pillar top and pillar sidewalls;
a channel region between the one and the another source/drain regions;
and
a conductive gate operatively proximate the channel region;
conducting-via constructions that are individually directly above and directly electrically coupled to the pillar of individual of the another source/drain regions;
digitlines that are individually above and directly electrically coupled to a plurality of the conducting-via constructions;
conductive-via constructions that are individually directly above and directly electrically coupled to the pillar of individual of the one source/drain regions;
storage elements that are individually electrically coupled to individual of the conductive-via constructions;
and
individual of the conducting-via constructions and the individual conductive-via constructions comprising a conductive monocrystalline covering that is directly above and directly against the pillar top and that is circumferentially about and directly against the pillar sidewalls, the conductive monocrystalline covering being of the same crystallinity as the conductively-doped monocrystalline semiconductive material of the pillar, the conductive monocrystalline covering at least predominantly having greater conductivity-increasing-dopant therein than is at least predominantly in the pillar top.

8 more elements

Memory circuitry comprising:

transistors individually comprising:
one source/drain region and another source/drain region, the one and another source/drain regions individually comprising a pillar comprising conductively-doped monocrystalline semiconductive material, the pillar comprising a pillar top and pillar sidewalls;
a channel region between the one and the another source/drain regions;
and
a conductive gate operatively proximate the channel region;
conducting-via constructions that are individually directly above and directly electrically coupled to the pillar of individual of the another source/drain regions;
digitlines that are individually above and directly electrically coupled to a plurality of the conducting-via constructions;
conductive-via constructions that are individually directly above and directly electrically coupled to the pillar of individual of the one source/drain regions;
storage elements that are individually electrically coupled to individual of the conductive-via constructions;
and
individual of the conducting-via constructions and the individual conductive-via constructions comprising:
a conductive monocrystalline covering that is directly above and directly against the pillar top and that is circumferentially about and directly against the pillar sidewalls;
and
an intermediate region at an interface of the conductive monocrystalline covering with the pillar top and the pillar sidewalls, the intermediate region comprising chlorine, fluorine, and nitrogen individually at 1×1015 atoms/cm3 to 5×1021 atoms/cm3.

11 more elements

Dependencies are inferred from the claim text.

Memory Circuitry And Methods Used In Forming Memory Circuitry

Life of this patent

Memory Circuitry And Methods Used In Forming Memory Circuitry

Life of this patent

Abstract

Claims22