Receiver circuit

A receiver circuit for processing pulse amplitude modulation (PAM) signalling that represents a stream of network symbols, wherein the receiver circuit is configured to receive:

• a network clock signal which corresponds to a network frequency;
• and
• a plurality of divided clock signals, wherein:
• each divided clock signal defines the same divided frequency as each other divided clock signal, wherein the divided frequency is an integer multiple of the network frequency, and
• each of the plurality of divided clock signals are phase offset with respect to each of the other divided clock frequencies, such that rising edges of each of the plurality of divided clock signals are evenly spaced apart from the rising edges of each other divided clock signal;
• wherein the receiver circuit comprises:
• a receiver output terminal;
• and
• a plurality of decision feedback equalizer sub-circuits, each associated with one of the divided clock signals, wherein:
• each decision feedback equalizer sub-circuit is configured to receive the PAM signalling that represents a current network symbol;
• each one of the plurality of decision feedback equalizer sub-circuits is configured for sequential generation of an output symbol;
• each of the decision feedback equalizer sub-circuit comprises:
• a first delay block that is configured to apply a delay to the PAM signalling in order to provide delayed PAM signalling, wherein the first delay block is clocked by the divided clock signal that is associated with the decision feedback equalizer sub-circuit;
• a coefficient application block that is configured to apply a plurality of coefficients to the delayed PAM signalling in order to provide processed PAM signalling, wherein each coefficient is based on one or more of a plurality of preceding output symbol values as provided by a sequence of the decision feedback equalizer sub-circuits;
• a slicer configured to apply one or more thresholds to the processed PAM signalling in order to provide a DFE-sub-circuit output symbol;
• and
• a second delay block that is configured to apply a delay to the DFE-sub-circuit output symbol in order to provide an output symbol, wherein the second delay block is clocked by the divided clock signal that is associated with the decision feedback equalizer sub-circuit;
• and
• a switching circuit that is configured to sequentially provide the output symbols that have been generated by each of the decision feedback equalizer sub-circuits as a stream of output symbols at the receiver output terminal.