Methods and apparatus for reducing pulse width distortion and/or delay
OwnerHimanth Mudda, Kumar Anurag Shrivastavainventors
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Abstract
An example electronic circuit includes: a first circuit having an input and an output, the first circuit configured to provide a first voltage at the output of the first circuit based on an input signal at the input of the first circuit, the output of the first circuit coupled to a first node; a clamp circuit comprising a memory element configured to store a value based on the first voltage, the clamp circuit configured to inject a first current into the first node based on the value to increase the first voltage at the first node; and a comparator configured to generate an output signal corresponding to the input signal based on a comparison of the first voltage at the first node to a reference voltage.
Claims22
An electronic circuit comprising:
- a first circuit having an input and an output, the first circuit configured to provide a first voltage at the output of the first circuit based on an input signal at the input of the first circuit, the output of the first circuit coupled to a first node;
- a clamp circuit comprising a memory element configured to store a value based on the first voltage, the clamp circuit configured to inject a first current into the first node based on the value to increase the first voltage at the first node;
- and
- a comparator configured to generate an output signal corresponding to the input signal based on a comparison of the first voltage at the first node to a reference voltage.
An apparatus comprising:
- a first supply voltage terminal;
- a second supply voltage terminal;
- a first transistor having first and second current path terminals, the first current path terminal of the first transistor coupled to the first supply voltage terminal, the second current path terminal of the first transistor coupled to the second supply voltage terminal;
- a first resistor coupled between the first supply voltage terminal and the first current path terminal of the first transistor;
- a comparator having a first input and a second input, the first input of the comparator coupled to the first current path terminal of the first transistor;
- a second transistor having a control terminal coupled to the second input of the comparator;
- a third transistor having a current path coupled to a current path of the second transistor;
- a fourth transistor having a control terminal coupled to a control terminal of the third transistor, and a current path coupled between the first supply voltage terminal and the first current path terminal of the first transistor;
- and
- a filter coupled between the control terminal of the third transistor and the control terminal of the fourth transistor.
Dependencies are inferred from the claim text.