Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsKentaro KIMOTO, Masafumi WATANABE, Satoshi ONISHI, Hidenori ORINO
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Abstract
Provided is a semiconductor device that suppresses an increase in an area and current of a PLL. An ADPL and an SPLL are included, and an SPD that compares an input signal with a feedback signal from a CCO, a charge pump circuit that outputs a current or a voltage based on a result of the SPD, a PFD that detects a phase difference which is a comparison result between the input signal and the feedback signal, and a phase difference digitizer that changes the current output by the charge pump circuit based on a detection result of the PFD are included.
Claims5
A semiconductor device comprising:
- a first phase-locked loop circuit including a first oscillator and a phase frequency control unit that performs phase control and frequency control on the first oscillator;
- and
- a second phase-locked loop circuit including a second oscillator whose frequency is controlled by a signal output from the phase frequency control unit, and a phase control unit that performs phase control on the second oscillator,
- wherein the second phase-locked loop circuit is composed of a sampling PLL, and
- wherein the phase control unit includes
- a first phase comparator that compares a phase of an input signal with a feedback signal from the second oscillator,
- a charge pump circuit that outputs a current based on a result of the first phase comparator, and
- a charge pump control circuit that changes a current output by the charge pump circuit based on a phase difference between the input signal and the feedback signal.
Dependencies are inferred from the claim text.