# US 2026/0074701 A1 · Systems and methods for dynamic power and thermal management for programmable logic devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0074701 A1 - Document ID: US20260074701A1 - Status: Published application - Kind: A1 - Application number: 19/392,124 - Filed: 2025-11-17 - Published: 2026-03-12 - Earliest claimed: 2022-04-01 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Mahesh K. Kumashikar; Ankireddy Nalamalpu; Atul Maheshwari; Lai Guan Tang - Web page: https://patentgrep.com/patent/US20260074701A1 ## CPC - H03K 19/17784: for supply voltage - G06F 1/206: {comprising thermal management} - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/324: by lowering clock frequency - G06F 1/3296: by lowering the supply or operating voltage - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/1776: for memories - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems or methods of the present disclosure may provide a programmable logic device including one or more power monitors and one or more thermal sensors. The programmable logic device may include control circuitry that may receive power data and thermal data for multiple die of the programmable logic device, and may implement one or more response based on the thermal and power data. ## Claims ### Claim 1 An electronic device package comprising: one or more voltage regulators; one or more thermal sensors to measure a thermal parameter; one or more compute die; and control circuitry to: determine a thermal level based on received thermal data; determine the thermal level exceeds one or more threshold values; and send instructions to one or more voltage regulators or one or more chiplets of the electronic device package to control thermal levels of the one or more compute die based on thermal data. ### Claim 2 (depends on 1) The electronic device package of claim 1, wherein the instructions comprise instructions to move one or more IO lanes of one or more IO chiplets of the one or more chiplets of the electronic device package to a low power state. ### Claim 3 (depends on 1) The electronic device package of claim 1, wherein the instructions comprise instructions to shut down one or more IO lanes of one or more IO chiplets of the one or more chiplets of the one or more compute die. ### Claim 4 (depends on 1) The electronic device package of claim 1, wherein the instructions comprise instructions to decrease an interface frequency of the one or more compute die, and send a communication to central control logic of the electronic device package to decrease interface logic traffic, wherein the central control logic comprises one or more processors and a memory. ### Claim 5 (depends on 1) The electronic device package of claim 1, wherein the instructions comprise instructions to lower a voltage frequency point of one or more accelerator chiplets of the one or more chiplets of the one or more compute die. ### Claim 6 (depends on 1) The electronic device package of claim 1, wherein the instructions comprise instructions to shut down one or more accelerator chiplets of the one or more chiplets of the one or more compute die. ### Claim 7 (depends on 1) The electronic device package of claim 1, wherein the thermal level comprises an average of the thermal parameter from a single thermal sensor over time. ### Claim 8 (depends on 1) The electronic device package of claim 1, wherein the thermal level comprises an average of the thermal parameters from multiple thermal sensors of the one or more thermal sensors. ### Claim 9 (depends on 1) The electronic device package of claim 1, wherein the thermal level comprises a peak thermal parameter. ### Claim 10 An electronic device package comprising: a plurality of compute die comprising a plurality of thermal sensors; and control circuitry to: receive thermal data from the plurality of thermal sensors located on the plurality of compute die; determine a hotspot in a first compute die using the thermal data; and cause programmable logic implemented in the hotspot to be implemented in a second compute die by reconfiguring one or more logic blocks from the first compute die to the second compute die. ### Claim 11 (depends on 10) The electronic device package of claim 10, wherein the plurality of compute die are stacked in a three-dimensional orientation. ### Claim 12 (depends on 10) The electronic device package of claim 10, wherein one or more thermal management controllers of the plurality of compute die is configured to send thermal data from the first compute die to the second compute die. ### Claim 13 (depends on 10) The electronic device package of claim 10, wherein the one or more logic blocks within each compute die are predefined as part of a modular design that has been previously compiled. ### Claim 14 (depends on 10) The electronic device package of claim 10, wherein reconfiguring the one or more logic blocks comprises loading the configuration from a configuration memory. ### Claim 15 (depends on 10) The electronic device package of claim 10, wherein reconfiguring the one or more logic blocks comprises compiling a design for the plurality of compute die when moving the hotspot from the first compute die. ### Claim 16 A programmable fabric device package comprising: one or more voltage regulators; one or more thermal sensors to measure a thermal parameter; one or more interconnected fabric die; and control circuitry to: determine a thermal level based on received thermal data; determine the thermal level exceeds one or more threshold values; and send instructions to one or more voltage regulators or one or more chiplets of the programmable fabric device to control thermal levels of the one or more interconnected fabric die based on thermal data. ### Claim 17 (depends on 16) The programmable fabric device package of claim 16, wherein the instructions comprise instructions to move one or more IO lanes of one or more IO chiplets of the one or more chiplets of the programmable fabric device to a low power state. ### Claim 18 (depends on 16) The programmable fabric device package of claim 16, wherein the instructions comprise instructions to shut down one or more IO lanes of one or more IO chiplets of the one or more chiplets of the one or more interconnected fabric die. ### Claim 19 (depends on 16) The programmable fabric device package of claim 16, wherein the instructions comprise instructions to decrease an interface frequency of the one or more interconnected fabric die, and send a communication to central control logic of the programmable fabric device package to decrease interface logic traffic, wherein the central control logic comprises one or more processors and a memory. ### Claim 20 (depends on 16) The programmable fabric device package of claim 16, wherein the instructions comprise instructions to lower a voltage frequency point of one or more accelerator chiplets of the one or more chiplets of the one or more interconnected fabric die.