Logic drive using standard commodity programmable logic ic chips
AssigneeiCometrue Company Ltd.
InventorsJin-Yuan Lee, Mou-Shiung Lin
Life of this patent
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Abstract
An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
Claims27
A multi-chip package comprising:
- an interconnection scheme comprising a first insulating dielectric layer, a first interconnection metal layer over the first insulating dielectric layer and a second insulating dielectric layer on the first interconnection metal layer and over the first insulating dielectric layer;
- a first semiconductor chip over the interconnection scheme, wherein the interconnection scheme is under the first semiconductor chip and across an edge of the first semiconductor chip, wherein the first semiconductor chip comprises a plurality of gate-all-around (GAA) field effective transistors (FETs), and wherein the first semiconductor chip comprises a first input/output (I/O) circuit configured to operate at a power supply voltage smaller than or equal to 0.7 volts;
- a first bonded contact vertically under the first semiconductor chip and between the first semiconductor chip and interconnection scheme, wherein the first bonded contact couples the first semiconductor chip to the interconnection scheme;
- a second semiconductor chip over the interconnection scheme, wherein the interconnection scheme is under the second semiconductor chip and across an edge of the second semiconductor chip, wherein the second semiconductor chip couples to the first input/output (I/O) circuit of the first semiconductor chip;
- and
- a first metal bump under the interconnection scheme and at a bottom of the multi-chip package.
Dependencies are inferred from the claim text.