Spurious suppression circuit

A method of spurious signal suppression, comprising:

• receiving, at a frequency discriminator having an insertion phase error proportional to an offset from a center frequency, a delay line output;
• providing, at the frequency discriminator, a discriminator output having a plurality of oscillatory modes;
• receiving, at a first phase shifter, the discriminator output;
• applying, at the first phase shifter, a phase shift compensating for a mixer port phase differential;
• providing, at a mixer, a mixer output having a DC component proportional to a phase difference between inputs received at first and second mixer ports, the first and second mixer ports being offset in phase by the mixer port phase differential, the first mixer port configured to receive the delay line output and the second mixer port configured to receive the discriminator output;
• receiving, at a second phase shifter, the mixer intermediate frequency output;
• providing, at the second phase shifter, a phase modulated signal;
• receiving, at a circuit coupler, the phase modulated signal;
• and
• providing, at the circuit coupler, a first circuit coupler output as an RF output of the circuit, and a second circuit coupler output as an input to the delay line.

A non-transient computer-readable storage medium having instructions embodied thereon, the instructions being executable by one or more processors to perform a method of spurious signal suppression, the method comprising:

• receiving, at a frequency discriminator having an insertion phase error proportional to an offset from a center frequency, a delay line output;
• providing, at the frequency discriminator, a discriminator output having a plurality of oscillatory modes;
• receiving, at a first phase shifter, the discriminator output;
• applying, at the first phase shifter, a phase shift compensating for a mixer port phase differential;
• providing, at a mixer, a mixer output having a DC component proportional to a phase difference between inputs received at first and second mixer ports, the first and second mixer ports being offset in phase by the mixer port phase differential, the first mixer port configured to receive the delay line output and the second mixer port configured to receive the discriminator output;
• receiving, at a second phase shifter, the mixer intermediate frequency output;
• providing, at the second phase shifter, a phase modulated signal;
• receiving, at a circuit coupler, phase modulated signal;
• and
• providing, at the circuit coupler, a first circuit coupler output as an RF output of the circuit, and a second circuit coupler output as an input to the delay line.

A circuit, comprising:

• a delay line configured to provide a delay line output;
• a voltage-controlled phase shifter configured to receive the delay line output and to phase modulate the delay line output based on a mixer output and to output a phase modulated signal;
• a first coupler configured to receive phase modulated signal and to generate a discriminator input signal and a mixer input signal;
• a frequency discriminator having an insertion phase error proportional to an offset from a center frequency, the frequency discriminator configured to receive the discriminator input signal and provide a discriminator output having a plurality of oscillatory modes;
• a second coupler configured to receive the discriminator output and to generate a first phase shifter input and a second coupler output;
• an electronic phase shifter configured to receive the first phase shifter input and apply a phase shift establishing a mixer port phase differential and to generate a first phase shifter output;
• a mixer configured to provide the mixer output for the voltage-controlled phase shifter, the mixer output having a DC component proportional to a phase difference between inputs received at first and second mixer ports, the first and second mixer ports being offset in phase by the mixer port phase differential, the first mixer port configured to receive the mixer input signal and the second mixer port configured to receive the first phase shifter output;
• an RF amplifier configured to receive the second coupler output, and output an amplified phase modulated signal to an input of the delay line;
• and
• a circuit coupler configured to receive the amplified phase modulated signal and to provide a first circuit coupler output as an RF output of the circuit, and to provide a second circuit coupler output as an input to the delay line.