System and methods for clock pulse generation
AssigneeCiena Corporation
InventorsNaftali Weiss, Jacob Pike, Philip Flemke, Michael Sawires, Shai Bonen, Euhan Chong
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Abstract
Aspects of the subject disclosure may include, for example, a track-and-hold sampling circuit, having: a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals; and a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal. Other embodiments are disclosed.
Claims20
A track-and-hold sampling circuit, comprising:
- a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals;
- and
- a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal.
A method for creating a duty-cycle clock signal for triggering a sampling circuit, comprising:
- applying a first clock signal to an n-type terminal of a T-gate, wherein the T-gate is a metal oxide semiconductor field effect transistor;
- applying a second clock signal to a p-type terminal of the T-gate;
- and
- applying a third clock signal to a gate of the T-gate, thereby creating the duty-cycle clock signal having a duty cycle that is less than 100%.
A track-and-hold sampling circuit, comprising:
- a first duty-cycle limiter that generates a first clock signal having a duty cycle that is less than 100% from three clock signals out of four clock signals supplied to the first duty-cycle limiter;
- a second duty-cycle limiter that generates a second clock signal having a second duty cycle that is less than 100% from another three out of the four clock signals, where one of clock signals is different from the three clock signals supplied to the first duty-cycle limiter;
- a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the first duty-cycle limiter through a first inverter;
- and
- a charge injection cancelation device that receives the sampled data signals and provides output data signals, wherein the charge injection cancelation device is triggered by an output of a second inverter connected to the second duty-cycle limiter.
Dependencies are inferred from the claim text.