# US 2026/0074656 A1 · Power amplification device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0074656 A1 - Document ID: US20260074656A1 - Status: Published application - Kind: A1 - Application number: 19/355,216 - Filed: 2025-10-10 - Published: 2026-03-12 - Earliest claimed: 2023-04-12 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Tetsurou ASHIDA; Kouhei Jitousho; Tomoya Oda; Shohei Imai - Web page: https://patentgrep.com/patent/US20260074656A1 ## CPC - H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers} - H03F 3/45085: {Long tailed pairs (H03F3/45112, H03F3/45139 take precedence)} - H03F 1/0266: {by using a signal derived from the input signal} - H03F 3/195: in integrated circuits - H03F 3/245: {with semiconductor devices only} - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03F 3/602: {Combinations of several amplifiers} - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F: AMPLIFIERS ## Abstract A power amplification device includes a substrate, a first integrated circuit, a second integrated circuit, a splitter, a carrier amplifier, a peak amplifier, a first bias circuit providing bias to the carrier amplifier, a second bias circuit providing bias to the peak amplifier, a drive-level detector circuit outputting a signal indicating a drive level of the carrier amplifier based on a high-frequency signal outputted by the carrier amplifier, a detector circuit that outputs a control signal to control the second bias circuit, based on an inputted high-frequency signal and the signal indicating the drive level of the carrier amplifier, and a coupler. The detector circuit varies a threshold for the control signal. The first integrated circuit includes the splitter, the first-stage carrier amplifier, the first-stage peak amplifier, and the detector circuit. The second integrated circuit includes the final-stage carrier amplifier and the final-stage peak amplifier. ## Claims ### Claim 1 A power amplification device, comprising: a substrate; a first integrated circuit on a major surface of the substrate; a second integrated circuit that is at a position different from the first integrated circuit on the major surface of the substrate and is coupled to the first integrated circuit via a plurality of wires in or on the substrate; a splitter; a carrier amplifier comprising a first-stage carrier amplifier configured to amplify an inputted high-frequency signal and a final-stage carrier amplifier configured to amplify a high-frequency signal outputted from the first-stage carrier amplifier; a peak amplifier comprising a first-stage peak amplifier configured to amplify the inputted high-frequency signal and a final-stage peak amplifier configured to amplify a high-frequency signal outputted from the first-stage peak amplifier; a first bias circuit configured to provide bias to the carrier amplifier; a second bias circuit configured to provide bias to the peak amplifier; a drive-level detector (DLD) circuit configured to output a signal indicating a drive level of the carrier amplifier, based on a high-frequency signal outputted by the carrier amplifier; a detector circuit configured to output a control signal configured to control the second bias circuit or the peak amplifier, based on the inputted high-frequency signal and the signal indicating the drive level of the carrier amplifier; and a coupler on the major surface of the substrate, wherein the detector circuit is configured to vary a threshold for the control signal based on the inputted high-frequency signal and the signal indicating the drive level of the carrier amplifier, wherein the first integrated circuit comprises the splitter, the first-stage carrier amplifier, the first-stage peak amplifier, and the detector circuit, wherein the second integrated circuit comprises the final-stage carrier amplifier and the final-stage peak amplifier, and wherein one of the plurality of wires is a DLD coupling wire coupled to the drive-level detector circuit. ### Claim 2 (depends on 1) The power amplification device according to claim 1, wherein an externally inputted high-frequency signal or the high-frequency signal inputted to the carrier amplifier is inputted to the detector circuit. ### Claim 3 (depends on 1) The power amplification device according to claim 1, wherein the drive-level detector circuit is included in the second integrated circuit, and wherein the DLD coupling wire is configured to transmit a signal outputted by the drive-level detector circuit. ### Claim 4 (depends on 1) The power amplification device according to claim 1, wherein the drive-level detector circuit is included in the first integrated circuit, and wherein the DLD coupling wire is configured to transmit a high-frequency signal to be inputted to the drive-level detector circuit. ### Claim 5 A power amplification device, comprising: a substrate; a first integrated circuit on a major surface of the substrate; a second integrated circuit that is at a position different from the first integrated circuit on the major surface of the substrate and is coupled to the first integrated circuit via a plurality of wires provided in or on the substrate; a splitter; a carrier amplifier comprising a first-stage carrier amplifier configured to amplify an inputted high-frequency signal and a final-stage carrier amplifier configured to amplify a high-frequency signal outputted from the first-stage carrier amplifier; a peak amplifier comprising a first-stage peak amplifier configured to amplify the inputted high-frequency signal and a final-stage peak amplifier configured to amplify a high-frequency signal outputted from the first-stage peak amplifier; a first bias circuit configured to provide bias to the carrier amplifier; a second bias circuit configured to provide bias to the peak amplifier; a drive-level detector (DLD) circuit configured to output a signal indicating a drive level of the carrier amplifier, based on a high-frequency signal outputted by the first bias circuit; a control circuit; and a coupler on the major surface of the substrate, wherein the first integrated circuit comprises the splitter, the first-stage carrier amplifier, the first-stage peak amplifier, and the control circuit, wherein the second integrated circuit comprises the final-stage carrier amplifier and the final-stage peak amplifier, wherein the control circuit comprises: a detector circuit configured to output a control signal configured to control the second bias circuit or the peak amplifier, and a variable attenuator configured to output to the detector circuit, based on the high-frequency signal inputted to the carrier amplifier and the signal indicating the drive level of the carrier amplifier, a high-frequency signal obtained by attenuating the inputted high-frequency signal, and wherein one of the plurality of wires is a DLD coupling wire that is coupled to the drive-level detector circuit. ### Claim 6 (depends on 5) The power amplification device according to claim 5, wherein the drive-level detector circuit is included in the second integrated circuit, and wherein the DLD coupling wire is configured to transmit a signal outputted by the drive-level detector circuit. ### Claim 7 (depends on 5) The power amplification device according to claim 5, wherein the drive-level detector circuit is included in the first integrated circuit, and wherein the DLD coupling wire is configured to transmits a high-frequency signal to be inputted to the drive-level detector circuit. ### Claim 8 (depends on 1) The power amplification device according to claim 1, wherein in plan view, the DLD coupling wire overlaps the final-stage carrier amplifier. ### Claim 9 (depends on 5) The power amplification device according to claim 5, wherein in plan view, the DLD coupling wire overlaps the final-stage carrier amplifier. ### Claim 10 (depends on 1) The power amplification device according to claim 1, wherein the substrate comprises: a first through via passing through a region of the substrate that overlaps at least a part of the final-stage carrier amplifier in plan view; and a second through via passing through a region of the substrate that overlaps at least a part of the final-stage peak amplifier in plan view, and wherein the DLD coupling wire is located between the region that overlaps the first through via and the region that overlaps the second through via in plan view. ### Claim 11 (depends on 5) The power amplification device according to claim 5, wherein the substrate comprises: a first through via passing through a region of the substrate that overlaps at least a part of the final-stage carrier amplifier in plan view; and a second through via passing through a region of the substrate that overlaps at least a part of the final-stage peak amplifier in plan view, and wherein the DLD coupling wire is located between the region that overlaps the first through via and the region that overlaps the second through via in plan view. ### Claim 12 (depends on 1) The power amplification device according to claim 1, wherein the substrate comprises a through via that passes through a region of the substrate that overlaps at least a part of the final-stage carrier amplifier and at least a part of the final-stage peak amplifier in plan view, and wherein the DLD coupling wire does not overlap the through via in plan view. ### Claim 13 (depends on 5) The power amplification device according to claim 5, wherein the substrate comprises a through via that passes through a region of the substrate that overlaps at least a part of the final-stage carrier amplifier and at least a part of the final-stage peak amplifier in plan view, and wherein the DLD coupling wire does not overlap the through via in plan view. ### Claim 14 (depends on 1) The power amplification device according to claim 1, wherein the final-stage carrier amplifier is a differential amplifier comprising a plurality of amplifiers. ### Claim 15 (depends on 5) The power amplification device according to claim 5, wherein the final-stage carrier amplifier is a differential amplifier comprising a plurality of amplifiers. ### Claim 16 (depends on 1) The power amplification device according to claim 1, wherein the first integrated circuit contains doped silicon, and wherein the second integrated circuit contains a compound semiconductor. ### Claim 17 (depends on 5) The power amplification device according to claim 5, wherein the first integrated circuit contains doped silicon, and wherein the second integrated circuit contains a compound semiconductor.