Semiconductor memory device and operating method thereof

An operating method of a memory device, comprising:

• generating, by a decoder, host data based on first input data and a first data bus inversion (DBI) signal, the first DBI signal indicating whether the first input data is inverted;
• generating, by a counter, a first counting value based on a number of bits with a first value in the first DBI signal;
• generating, by an indicator generation circuit, an indicator signal having one bit based on the first counting value;
• generating, by an inverter, inverted host data by inverting all bits of the host data;
• and
• selecting and outputting, by a data selection circuit, the host data or the inverted host data as write data based on the indicator signal.

A memory device comprising:

• a decoder configured to
• receive first input data that is based on host data and a first data bus inversion (DBI) signal indicating whether the first input data is inverted, and
• output the host data;
• an inverter configured to generate inverted host data by inverting all bits of the host data;
• a counter configured to count a number of bits with a first value in the first DBI signal;
• an indicator generation circuit configured to generate an indicator signal based on a first counting value indicative of the number of bits with the first value in the first DBI signal;
• an error correction code (ECC) circuit configured to receive the host data and a default indicator signal and output parity bits;
• a data selection circuit configured to receive the host data and the inverted host data, in response to the indicator signal, select the host data or the inverted host data as write data;
• and
• a memory cell array configured to store (i) the write data;
• (ii) the indicator signal;
• and (iii) the parity bits or updated parity bits.